| Message ID | cover.1639660956.git.geert@linux-m68k.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | riscv: dts: Miscellaneous fixes | expand |
From: Biju Das <biju.das.jz@bp.renesas.com>
RZ/G2L SoC embeds Mali-G31 bifrost GPU.
This patch series aims to add support for the same
It is tested with latest drm-misc-next + mesa 21.3.0 +
out of tree patch for (du + DSI) +
platform specific mesa configuration for RZ/G2L.
Tested the kmscube application.
test logs:-
root@smarc-rzg2l:~# kmscube
Using display 0xaaaadb6e7d30 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
....
===================================
^C
root@smarc-rzg2l:~# cat /proc/interrupts | grep panfrost
82: 587287 0 GICv3 186 Level panfrost-job
83: 2 0 GICv3 187 Level panfrost-mmu
84: 8 0 GICv3 185 Level panfrost-gpu
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 0 72
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 0 0
125000000: 0 0 0 0 0 0 0 1 68
200000000: 0 0 0 0 0 0 0 1 68
250000000: 1 0 0 0 0 0 0 0 84
400000000: 0 0 0 0 0 0 0 0 0
500000000: 0 0 0 1 1 1 0 0 736
Total transition : 6
root@smarc-rzg2l:~# kmscube
Using display 0xaaaaf7a421b0 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
......
===================================
root@smarc-rzg2l:~#
root@smarc-rzg2l:~#
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 1 144
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 9 524
125000000: 0 0 9 0 0 0 0 3 2544
200000000: 0 0 0 11 0 0 0 46 3304
250000000: 1 0 0 0 33 0 0 0 7496
400000000: 0 0 0 0 16 19 0 0 2024
500000000: 1 0 0 1 8 15 35 0 4032
Total transition : 208
Platform specific mesa configuration patch for RZ/G2L
---------------------
src/gallium/targets/dri/meson.build
+ 'rcar-du_dri.so',
src/gallium/targets/dri/target.c
+DEFINE_LOADER_DRM_ENTRYPOINT(rcar_du)
V2->V3:
* Moved optional clock-names and reset-names to SoC-specific conditional schemas.
* minimum number of reset for the generic GPU is set to 1.
* Documented number of clocks, resets, interrupts and interrupt-names in RZ/G2L
SoC-specific conditional schemas.
* Updated commit description for patch#3
V1->V2:
* Removed clock patches from this seies, as it is accepted for 5.17
* Added Rb tag from Geert
* Added reset-names required property for RZ/G2L and updated the board dtsi.
Biju Das (3):
dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
.../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 65 +++++++++++++++++++
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 ++++
3 files changed, 121 insertions(+), 2 deletions(-)
From: Miquel Raynal <miquel.raynal@bootlin.com>
Hello,
Here is a short series bringing support for Renesas RZ/N1 NAND
controller.
This time the driver has been tested with a fully-upstream device tree
on top of a v5.16-rc4. The DT used is very close to the r9a06g032-db.
Cheers,
Miquèl
Changes in v4:
* Set unevaluatedProperties set to false in the bindings.
* Change the clock names by removing the nand_ prefix which is
redundant, even though the clocks are named like this in the spec. The
name remains clear enough anyway.
Changes in v3:
* Rebased on top of a fully-upstream recent kernel.
* Renamed the clocks in the bindings and the driver to match the
documentation (lower-cased): nand_hclk & nand_eclk.
* Added a new commit describing the NAND controller in the r9a06g032
DTSI.
* Added the Reviewed-by and Tested-by tags received.
Changes in v2:
* Added the family-specific rzn1 compatible as suggested by Geert.
Updated the bindings, the binding file name, the compatible used in
the driver, the MAINTAINERS entry, etc.
* Added an ARCH_RENESAS Kconfig dependency.
* Changed the type (to unsigned) of a couple of variables.
* Returned earlier when possible to reduce indentation.
* Used platform_get_irq_optional() instead of platform_get_irq() to avoid
a useless warning.
* Handled probe deferral correctly.
* Applied a massive s/nfc/nandc/ as suggested by Geert to avoid
confusions with the near-field-communication device.
* Mentioned Evatronix as original authors of the IP in the commit log and
in the header.
* Added an additional check on the validity of the child nodes reg property.
* A couple of style fixes.
Miquel Raynal (4):
dt-bindings: mtd: rzn1: Describe Renesas RZ/N1 NAND controller
mtd: rawnand: rzn1: Add new NAND controller driver
MAINTAINERS: Add an entry for Renesas RZ/N1 NAND controller
ARM: dts: r9a06g032: Describe NAND controller
.../mtd/renesas,rzn1-nand-controller.yaml | 64 +
MAINTAINERS | 7 +
arch/arm/boot/dts/r9a06g032.dtsi | 12 +
drivers/mtd/nand/raw/Kconfig | 6 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/rzn1-nand-controller.c | 1422 +++++++++++++++++
6 files changed, 1512 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml
create mode 100644 drivers/mtd/nand/raw/rzn1-nand-controller.c
Hi Paul, Palmer, Albert, This patch series contains miscellaneous fixes for the DTS files for RISC-V platforms. Changes compared to v1[1]: - Add Reviewed-by, Tested-by, - Move mpfs refclk clock-frequency to board DTS, - New patches "[PATCH v2 06/11] riscv: dts: microchip: mpfs: Fix clock controller node" and "[PATCH v2 11/11] riscv: dts: sifive: fu540-c000: Fix PLIC node". Thanks for applying! [1] https://lore.kernel.org/r/20211125153131.163533-1-geert@linux-m68k.org Geert Uytterhoeven (11): riscv: dts: canaan: Fix SPI FLASH node names riscv: dts: canaan: Group tuples in interrupt properties riscv: dts: microchip: mpfs: Drop empty chosen node riscv: dts: microchip: mpfs: Fix PLIC node riscv: dts: microchip: mpfs: Fix reference clock node riscv: dts: microchip: mpfs: Fix clock controller node riscv: dts: microchip: mpfs: Group tuples in interrupt properties riscv: dts: sifive: Group tuples in interrupt properties riscv: dts: sifive: Group tuples in register properties riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values riscv: dts: sifive: fu540-c000: Fix PLIC node arch/riscv/boot/dts/canaan/k210.dtsi | 23 +++---- .../riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +- .../boot/dts/canaan/sipeed_maix_dock.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +- .../boot/dts/canaan/sipeed_maixduino.dts | 2 +- .../microchip/microchip-mpfs-icicle-kit.dts | 4 ++ .../boot/dts/microchip/microchip-mpfs.dtsi | 60 ++++++++----------- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 40 +++++++------ arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 14 ++--- 9 files changed, 72 insertions(+), 77 deletions(-)