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[v2,0/1] RISC-V: clarification of the QEMU workaround in the ISA parser

Message ID cover.1690350252.git.research_trasio@irq.a4lg.com (mailing list archive)
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Series RISC-V: clarification of the QEMU workaround in the ISA parser | expand

Message

Tsukasa OI July 26, 2023, 5:44 a.m. UTC 
Hello,

This is the PATCH v2 to clarify the intent and a non-working example of the
QEMU workaround in the RISC-V ISA parser.  Along with comment fixes, I hope
the commit message itself should be helpful to understand the workaround
in the ISA string parser.

v1:
(the initial submission; see the each PATCH for details)

v2:
*   PATCH 1/2 is withdrawn for now
    (now only comment fix; previously PATCH 2/2)
*   Other grammar fixes
*   Clarification of the commit message




Tsukasa OI (1):
  RISC-V: clarify the QEMU workaround in ISA parser

 arch/riscv/kernel/cpufeature.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)