Show patches with: Series = [01/20] irqchip/sifive-plic: set max threshold for ignored handlers       |    State = Action Required       |   20 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[20/20] riscv: disable the EFI PECOFF header for M-mode [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - - - --- 2019-09-03 Christoph Hellwig New
[19/20] riscv: provide a flat image loader [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - - - --- 2019-09-03 Christoph Hellwig New
[18/20] riscv: add nommu support [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - - - --- 2019-09-03 Christoph Hellwig New
[17/20] riscv: clear the instruction cache and all registers when booting [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - - - --- 2019-09-03 Christoph Hellwig New
[16/20] riscv: use the correct interrupt levels for M-mode [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - - - --- 2019-09-03 Christoph Hellwig New
[15/20] riscv: read the hart ID from mhartid on boot [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - 1 - --- 2019-09-03 Christoph Hellwig New
[14/20] riscv: provide native clint access for M-mode [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - - - --- 2019-09-03 Christoph Hellwig New
[13/20] riscv: add support for MMIO access to the timer registers [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - - - --- 2019-09-03 Christoph Hellwig New
[12/20] riscv: implement remote sfence.i using IPIs [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - - - --- 2019-09-03 Christoph Hellwig New
[11/20] riscv: cleanup the default power off implementation [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - 1 - --- 2019-09-03 Christoph Hellwig New
[10/20] riscv: poison SBI calls for M-mode [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - - - --- 2019-09-03 Christoph Hellwig New
[09/20] riscv: don't allow selecting SBI based drivers for M-mode [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - - - --- 2019-09-03 Christoph Hellwig New
[08/20] riscv: abstract out CSR names for supervisor vs machine mode [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - 1 - --- 2019-09-03 Christoph Hellwig New
[07/20] riscv: move the TLB flush logic out of line [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - 1 - --- 2019-09-03 Christoph Hellwig New
[06/20] riscv: don't use the rdtime(h) pseudo-instructions [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - 1 - --- 2019-09-03 Christoph Hellwig New
[05/20] riscv: cleanup riscv_cpuid_to_hartid_mask [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - 1 - --- 2019-09-03 Christoph Hellwig New
[04/20] riscv: optimize send_ipi_single [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - 1 - --- 2019-09-03 Christoph Hellwig New
[03/20] riscv: cleanup send_ipi_mask [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - 1 - --- 2019-09-03 Christoph Hellwig New
[02/20] riscv: refactor the IPI code [01/20] irqchip/sifive-plic: set max threshold for ignored handlers - 1 - --- 2019-09-03 Christoph Hellwig New
[01/20] irqchip/sifive-plic: set max threshold for ignored handlers [01/20] irqchip/sifive-plic: set max threshold for ignored handlers 1 - - --- 2019-09-03 Christoph Hellwig New