Show patches with: Submitter = Andrew Jones       |    Archived = No       |   300 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v3,03/13] RISC-V: paravirt: Implement steal-time support RISC-V: Add steal-time support - 2 - --1 2023-12-17 Andrew Jones Superseded
[v3,02/13] RISC-V: Add SBI STA extension definitions RISC-V: Add steal-time support - 3 - --1 2023-12-17 Andrew Jones Superseded
[v3,01/13] RISC-V: paravirt: Add skeleton for pv-time support RISC-V: Add steal-time support - 2 - --1 2023-12-17 Andrew Jones Superseded
[v2,13/13] RISC-V: KVM: selftests: Add get-reg-list test for STA registers RISC-V: Add steal-time support - 1 - --- 2023-12-14 Andrew Jones Superseded
[v2,12/13] RISC-V: KVM: selftests: Add steal_time test support RISC-V: Add steal-time support - 1 - --- 2023-12-14 Andrew Jones Superseded
[v2,11/13] RISC-V: KVM: selftests: Add guest_sbi_probe_extension RISC-V: Add steal-time support - 1 - --- 2023-12-14 Andrew Jones Superseded
[v2,10/13] RISC-V: KVM: selftests: Move sbi_ecall to processor.c RISC-V: Add steal-time support - 2 - --- 2023-12-14 Andrew Jones Superseded
[v2,09/13] RISC-V: KVM: Implement SBI STA extension RISC-V: Add steal-time support - 1 - --- 2023-12-14 Andrew Jones Superseded
[v2,08/13] RISC-V: KVM: Add support for SBI STA registers RISC-V: Add steal-time support - 2 - --- 2023-12-14 Andrew Jones Superseded
[v2,07/13] RISC-V: KVM: Add support for SBI extension registers RISC-V: Add steal-time support - 1 - --- 2023-12-14 Andrew Jones Superseded
[v2,06/13] RISC-V: KVM: Add SBI STA info to vcpu_arch RISC-V: Add steal-time support - 1 - --- 2023-12-14 Andrew Jones Superseded
[v2,05/13] RISC-V: KVM: Add steal-update vcpu request RISC-V: Add steal-time support - 1 - --- 2023-12-14 Andrew Jones Superseded
[v2,04/13] RISC-V: KVM: Add SBI STA extension skeleton RISC-V: Add steal-time support - 1 - --- 2023-12-14 Andrew Jones Superseded
[v2,03/13] RISC-V: paravirt: Implement steal-time support RISC-V: Add steal-time support - - - --- 2023-12-14 Andrew Jones Superseded
[v2,02/13] RISC-V: Add SBI STA extension definitions RISC-V: Add steal-time support - 2 - --- 2023-12-14 Andrew Jones Superseded
[v2,01/13] RISC-V: paravirt: Add skeleton for pv-time support RISC-V: Add steal-time support - 1 - --- 2023-12-14 Andrew Jones Superseded
[v2,6/6] RISC-V: KVM: selftests: Treat SBI ext regs like ISA ext regs RISC-V: KVM: Make SBI uapi consistent with ISA uapi - 1 - --- 2023-12-13 Andrew Jones Handled Elsewhere
[v2,5/6] KVM: riscv: selftests: Use register subtypes RISC-V: KVM: Make SBI uapi consistent with ISA uapi - 2 - --- 2023-12-13 Andrew Jones Handled Elsewhere
[v2,4/6] KVM: riscv: selftests: Add RISCV_SBI_EXT_REG RISC-V: KVM: Make SBI uapi consistent with ISA uapi - 1 - --- 2023-12-13 Andrew Jones Handled Elsewhere
[v2,3/6] RISC-V: KVM: Make SBI uapi consistent with ISA uapi RISC-V: KVM: Make SBI uapi consistent with ISA uapi - 1 - --- 2023-12-13 Andrew Jones Handled Elsewhere
[v2,2/6] KVM: riscv: selftests: Drop SBI multi registers RISC-V: KVM: Make SBI uapi consistent with ISA uapi - 1 - --- 2023-12-13 Andrew Jones Handled Elsewhere
[v2,1/6] RISC-V: KVM: Don't add SBI multi regs in get-reg-list RISC-V: KVM: Make SBI uapi consistent with ISA uapi - 2 - --- 2023-12-13 Andrew Jones Handled Elsewhere
[v3,1/1] riscv: sbi: Introduce system suspend support riscv: Introduce system suspend support - 1 1 13-- 2023-12-06 Andrew Jones Accepted
[v1,14/14] RISC-V: KVM: selftests: Add get-reg-list test for STA registers RISC-V: Add steal-time support - - - --1 2023-12-05 Andrew Jones Superseded
[v1,13/14] RISC-V: KVM: selftests: Add steal_time test support RISC-V: Add steal-time support - - - --1 2023-12-05 Andrew Jones Superseded
[v1,12/14] RISC-V: KVM: selftests: Add guest_sbi_probe_extension RISC-V: Add steal-time support - - - --1 2023-12-05 Andrew Jones Superseded
[v1,11/14] RISC-V: KVM: selftests: Move sbi_ecall to processor.c RISC-V: Add steal-time support - - - --1 2023-12-05 Andrew Jones Superseded
[v1,10/14] RISC-V: KVM: Implement SBI STA extension RISC-V: Add steal-time support - - - --1 2023-12-05 Andrew Jones Superseded
[v1,09/14] RISC-V: KVM: Add support for SBI STA registers RISC-V: Add steal-time support - - - --1 2023-12-05 Andrew Jones Superseded
[v1,08/14] RISC-V: KVM: Add support for SBI extension registers RISC-V: Add steal-time support - - - --1 2023-12-05 Andrew Jones Superseded
[v1,07/14] RISC-V: KVM: Add SBI STA info to vcpu_arch RISC-V: Add steal-time support - - - --1 2023-12-05 Andrew Jones Superseded
[v1,06/14] RISC-V: KVM: Add steal-update vcpu request RISC-V: Add steal-time support - - - --1 2023-12-05 Andrew Jones Superseded
[v1,05/14] RISC-V: KVM: Add SBI STA extension skeleton RISC-V: Add steal-time support - - - --1 2023-12-05 Andrew Jones Superseded
[v1,04/14] RISC-V: paravirt: Add kconfigs RISC-V: Add steal-time support - 1 - --1 2023-12-05 Andrew Jones Superseded
[v1,03/14] RISC-V: paravirt: Implement steal-time support RISC-V: Add steal-time support - - - --1 2023-12-05 Andrew Jones Superseded
[v1,02/14] RISC-V: Add SBI STA extension definitions RISC-V: Add steal-time support - 1 - --1 2023-12-05 Andrew Jones Superseded
[v1,01/14] RISC-V: paravirt: Add skeleton for pv-time support RISC-V: Add steal-time support - - - --1 2023-12-05 Andrew Jones Superseded
[6/6] RISC-V: KVM: selftests: Treat SBI ext regs like ISA ext regs RISC-V: KVM: Make SBI uapi consistent with ISA uapi - - - --1 2023-11-30 Andrew Jones Superseded
[5/6] KVM: riscv: selftests: Use register subtypes RISC-V: KVM: Make SBI uapi consistent with ISA uapi - 1 - --1 2023-11-30 Andrew Jones Superseded
[4/6] KVM: riscv: selftests: Add RISCV_SBI_EXT_REG RISC-V: KVM: Make SBI uapi consistent with ISA uapi - - - --1 2023-11-30 Andrew Jones Superseded
[2/6] KVM: riscv: selftests: Drop SBI multi registers RISC-V: KVM: Make SBI uapi consistent with ISA uapi - - - --1 2023-11-30 Andrew Jones Superseded
[1/6] RISC-V: KVM: Don't add SBI multi regs in get-reg-list RISC-V: KVM: Make SBI uapi consistent with ISA uapi - 1 - --1 2023-11-30 Andrew Jones Superseded
[v2,1/1] riscv: sbi: Introduce system suspend support riscv: Introduce system suspend support - - 1 13-- 2023-11-29 Andrew Jones Superseded
RISC-V: selftests: Fix compiler warnings RISC-V: selftests: Fix compiler warnings - - - 112- 2023-11-22 Andrew Jones Superseded
[v3,4/4] RISC-V: selftests: Add which-cpus hwprobe test RISC-V: hwprobe: Introduce which-cpus - 1 - 1111 2023-11-22 Andrew Jones Accepted
[v3,3/4] RISC-V: hwprobe: Introduce which-cpus flag RISC-V: hwprobe: Introduce which-cpus - 1 - 1111 2023-11-22 Andrew Jones Accepted
[v3,2/4] RISC-V: Move the hwprobe syscall to its own file RISC-V: hwprobe: Introduce which-cpus - 1 - 1111 2023-11-22 Andrew Jones Accepted
[v3,1/4] RISC-V: hwprobe: Clarify cpus size parameter RISC-V: hwprobe: Introduce which-cpus - 2 - 12-1 2023-11-22 Andrew Jones Accepted
[-next] RISC-V: hwprobe: Always use u64 for extension bits [-next] RISC-V: hwprobe: Always use u64 for extension bits - - - 13-- 2023-11-01 Andrew Jones Accepted
[v2,6/6] RISC-V: selftests: Add which-cpus hwprobe test RISC-V: hwprobe: Introduce which-cpus - 1 - --1 2023-10-20 Andrew Jones Superseded
[v2,5/6] RISC-V: selftests: Convert hwprobe test to kselftest API RISC-V: hwprobe: Introduce which-cpus - - - --1 2023-10-20 Andrew Jones Superseded
[v2,4/6] RISC-V: selftests: Statically link hwprobe test RISC-V: hwprobe: Introduce which-cpus - 1 - --1 2023-10-20 Andrew Jones Superseded
[v2,3/6] RISC-V: hwprobe: Introduce which-cpus flag RISC-V: hwprobe: Introduce which-cpus - - - --1 2023-10-20 Andrew Jones Superseded
[v2,2/6] RISC-V: Move the hwprobe syscall to its own file RISC-V: hwprobe: Introduce which-cpus - 1 - --1 2023-10-20 Andrew Jones Superseded
[v2,1/6] RISC-V: hwprobe: Clarify cpus size parameter RISC-V: hwprobe: Introduce which-cpus - 2 - --1 2023-10-20 Andrew Jones Superseded
[v1,1/1] riscv: sbi: Introduce system suspend support riscv: Introduce system suspend support - - 1 14-- 2023-10-12 Andrew Jones Superseded
[v1,6/6] RISC-V: selftests: Add which-cpus hwprobe test RISC-V: hwprobe: Introduce which-cpus - 1 - --1 2023-10-11 Andrew Jones Superseded
[v1,5/6] RISC-V: selftests: Convert hwprobe test to kselftest API RISC-V: hwprobe: Introduce which-cpus - - - --1 2023-10-11 Andrew Jones Superseded
[v1,4/6] RISC-V: selftests: Statically link hwprobe test RISC-V: hwprobe: Introduce which-cpus - 1 - --1 2023-10-11 Andrew Jones Superseded
[v1,3/6] RISC-V: hwprobe: Introduce which-cpus flag RISC-V: hwprobe: Introduce which-cpus - - - --1 2023-10-11 Andrew Jones Superseded
[v1,2/6] RISC-V: Move the hwprobe syscall to its own file RISC-V: hwprobe: Introduce which-cpus - - - --1 2023-10-11 Andrew Jones Superseded
[v1,1/6] RISC-V: hwprobe: Clarify cpus size parameter RISC-V: hwprobe: Introduce which-cpus - 2 - --1 2023-10-11 Andrew Jones Superseded
RISC-V: hwprobe: Fix vDSO SIGSEGV RISC-V: hwprobe: Fix vDSO SIGSEGV - 1 - 14-- 2023-10-10 Andrew Jones Accepted
KVM: riscv: selftests: get-reg-list print_reg should never fail KVM: riscv: selftests: get-reg-list print_reg should never fail - 1 - 151- 2023-09-20 Andrew Jones Handled Elsewhere
[v4,6/6] RISC-V: selftests: Add CBO tests RISC-V: Enable cbo.zero in usermode - 1 - 273- 2023-09-18 Andrew Jones Accepted
[v4,5/6] RISC-V: selftests: Convert hwprobe test to kselftest API RISC-V: Enable cbo.zero in usermode - - - 273- 2023-09-18 Andrew Jones Accepted
[v4,4/6] RISC-V: selftests: Statically link hwprobe test RISC-V: Enable cbo.zero in usermode - 1 - 291- 2023-09-18 Andrew Jones Accepted
[v4,3/6] RISC-V: hwprobe: Expose Zicboz extension and its block size RISC-V: Enable cbo.zero in usermode - 2 - 273- 2023-09-18 Andrew Jones Accepted
[v4,2/6] RISC-V: Enable cbo.zero in usermode RISC-V: Enable cbo.zero in usermode - 1 - 273- 2023-09-18 Andrew Jones Accepted
[v4,1/6] RISC-V: Make zicbom/zicboz errors consistent RISC-V: Enable cbo.zero in usermode - 1 - 291- 2023-09-18 Andrew Jones Accepted
[v3,6/6] RISC-V: selftests: Add CBO tests RISC-V: Enable cbo.zero in usermode - - - 151- 2023-09-04 Andrew Jones Superseded
[v3,5/6] RISC-V: selftests: Convert hwprobe test to kselftest API RISC-V: Enable cbo.zero in usermode - - - 151- 2023-09-04 Andrew Jones Superseded
[v3,4/6] RISC-V: selftests: Statically link hwprobe test RISC-V: Enable cbo.zero in usermode - 1 - 16-- 2023-09-04 Andrew Jones Superseded
[v3,3/6] RISC-V: hwprobe: Expose Zicboz extension and its block size RISC-V: Enable cbo.zero in usermode - 2 - 151- 2023-09-04 Andrew Jones Superseded
[v3,2/6] RISC-V: Enable cbo.zero in usermode RISC-V: Enable cbo.zero in usermode - 1 - 151- 2023-09-04 Andrew Jones Superseded
[v3,1/6] RISC-V: Make zicbom/zicboz errors consistent RISC-V: Enable cbo.zero in usermode - 1 - 16-- 2023-09-04 Andrew Jones Superseded
[v2,6/6] RISC-V: selftests: Add CBO tests RISC-V: Enable cbo.zero in usermode - - - --1 2023-08-30 Andrew Jones Superseded
[v2,5/6] RISC-V: selftests: Convert hwprobe test to kselftest API RISC-V: Enable cbo.zero in usermode - - - --1 2023-08-30 Andrew Jones Superseded
[v2,4/6] RISC-V: selftests: Statically link hwprobe test RISC-V: Enable cbo.zero in usermode - 1 - --1 2023-08-30 Andrew Jones Superseded
[v2,3/6] RISC-V: hwprobe: Expose Zicboz extension and its block size RISC-V: Enable cbo.zero in usermode - 2 - --1 2023-08-30 Andrew Jones Superseded
[v2,2/6] RISC-V: Enable cbo.zero in usermode RISC-V: Enable cbo.zero in usermode - 1 - --1 2023-08-30 Andrew Jones Superseded
[v2,1/6] RISC-V: Make zicbom/zicboz errors consistent RISC-V: Enable cbo.zero in usermode - 1 - --1 2023-08-30 Andrew Jones Superseded
[2/2] KVM: selftests: Add array order helpers to riscv get-reg-list RISC-V: KVM: A couple kselftests improvements - 1 - --1 2023-08-17 Andrew Jones Handled Elsewhere
[1/2] MAINTAINERS: RISC-V: KVM: Add another kselftests path RISC-V: KVM: A couple kselftests improvements - 1 - --1 2023-08-17 Andrew Jones Handled Elsewhere
[6/6] RISC-V: selftests: Add CBO tests RISC-V: Enable cbo.zero in usermode - - - 151- 2023-08-09 Andrew Jones Superseded
[5/6] RISC-V: selftests: Convert hwprobe test to kselftest API RISC-V: Enable cbo.zero in usermode - - - 151- 2023-08-09 Andrew Jones Superseded
[4/6] RISC-V: selftests: Statically link hwprobe test RISC-V: Enable cbo.zero in usermode - 1 - 16-- 2023-08-09 Andrew Jones Superseded
[3/6] RISC-V: hwprobe: Expose Zicboz extension and its block size RISC-V: Enable cbo.zero in usermode - 1 - 151- 2023-08-09 Andrew Jones Superseded
[2/6] RISC-V: Enable cbo.zero in usermode RISC-V: Enable cbo.zero in usermode - - - 1411 2023-08-09 Andrew Jones Superseded
[1/6] RISC-V: Make zicbom/zicboz errors consistent RISC-V: Enable cbo.zero in usermode - 1 - 16-- 2023-08-09 Andrew Jones Superseded
RISC-V: KVM: Improve vector save/restore functions RISC-V: KVM: Improve vector save/restore functions - 1 - --1 2023-08-04 Andrew Jones Handled Elsewhere
[v3,3/3] RISC-V: KVM: Probe for SBI extension status RISC-V: KVM: Ensure SBI extension is enabled - 1 - 16-- 2023-05-30 Andrew Jones Handled Elsewhere
[v3,2/3] RISC-V: KVM: Convert extension_disabled[] to ext_status[] RISC-V: KVM: Ensure SBI extension is enabled - 1 - 16-- 2023-05-30 Andrew Jones Handled Elsewhere
[v3,1/3] RISC-V: KVM: Rename dis_idx to ext_idx RISC-V: KVM: Ensure SBI extension is enabled - 1 - 16-- 2023-05-30 Andrew Jones Handled Elsewhere
[v2,3/3] RISC-V: KVM: Probe for SBI extension status RISC-V: KVM: Ensure SBI extension is enabled - 1 - 16-- 2023-05-26 Andrew Jones Superseded
[v2,2/3] RISC-V: KVM: Convert extension_disabled[] to ext_status[] RISC-V: KVM: Ensure SBI extension is enabled - 1 - 16-- 2023-05-26 Andrew Jones Superseded
[v2,1/3] RISC-V: KVM: Rename dis_idx to ext_idx RISC-V: KVM: Ensure SBI extension is enabled - 1 - 16-- 2023-05-26 Andrew Jones Superseded
[v2] RISC-V: Align SBI probe implementation with spec [v2] RISC-V: Align SBI probe implementation with spec - 1 - 17-- 2023-04-27 Andrew Jones Accepted
RISC-V: Align SBI probe implementation with spec RISC-V: Align SBI probe implementation with spec - 1 - 17-- 2023-04-26 Andrew Jones Superseded
[3/3] RISC-V: KVM: Introduce extension_enabled RISC-V: KVM: Ensure SBI extension is enabled - - - --1 2023-04-26 Andrew Jones Superseded
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