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Patch Series A/R/T S/W/F Date Submitter Delegate State
[3/9] riscv: remove CONFIG_RISCV_ISA_A [1/9] riscv: use asm-generic/extable.h - - - --- 2019-04-11 Christoph Hellwig New
[2/9] riscv: remove dead big endian code [1/9] riscv: use asm-generic/extable.h - - - --- 2019-04-11 Christoph Hellwig New
[1/9] riscv: use asm-generic/extable.h [1/9] riscv: use asm-generic/extable.h - 1 - --- 2019-04-11 Christoph Hellwig New
[v4,2/2] tty: serial: add driver for the SiFive UART tty: serial: add DT bindings and serial driver for the SiFive FU540 UART - - - --- 2019-04-11 Paul Walmsley New
[v4,1/2] dt-bindings: serial: add documentation for the SiFive UART driver tty: serial: add DT bindings and serial driver for the SiFive FU540 UART - - - --- 2019-04-11 Paul Walmsley New
[6/6] riscv: defconfig: enable ARCH_SIFIVE [1/6] arch: riscv: add support for building DTB files from DT source data - - - --- 2019-04-11 Paul Walmsley New
[5/6] riscv: dts: add initial board data for the SiFive HiFive Unleashed [1/6] arch: riscv: add support for building DTB files from DT source data - - - --- 2019-04-11 Paul Walmsley New
[4/6] riscv: dts: add initial support for the SiFive FU540-C000 SoC [1/6] arch: riscv: add support for building DTB files from DT source data - - - --- 2019-04-11 Paul Walmsley New
[3/6] dt-bindings: riscv: convert cpu binding to json-schema [1/6] arch: riscv: add support for building DTB files from DT source data - - - --- 2019-04-11 Paul Walmsley New
[2/6] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540 [1/6] arch: riscv: add support for building DTB files from DT source data - - - --- 2019-04-11 Paul Walmsley New
[1/6] arch: riscv: add support for building DTB files from DT source data [1/6] arch: riscv: add support for building DTB files from DT source data - - 1 --- 2019-04-11 Paul Walmsley New
[v3,3/3] clk: sifive: add a driver for the SiFive FU540 PRCI IP block clk: add driver for the SiFive FU540 PRCI and PLLs it controls - - - --- 2019-04-11 Paul Walmsley New
[v3,2/3] dt-bindings: clk: add documentation for the SiFive PRCI driver clk: add driver for the SiFive FU540 PRCI and PLLs it controls - 1 - --- 2019-04-11 Paul Walmsley New
[v3,1/3] clk: analogbits: add Wide-Range PLL library clk: add driver for the SiFive FU540 PRCI and PLLs it controls - - - --- 2019-04-11 Paul Walmsley New
[v2,4/4] RISC-V: Support nr_cpus command line option. Miscellaneous kernel command line fixes - - - --- 2019-04-10 Atish Patra New
[v2,3/4] RISC-V: Implement nosmp commandline option. Miscellaneous kernel command line fixes - - - --- 2019-04-10 Atish Patra New
[v2,2/4] RISC-V: Fix of_get_cpu_node usage Miscellaneous kernel command line fixes - - - --- 2019-04-10 Atish Patra New
[v2,1/4] RISC-V: Add RISC-V specific arch_match_cpu_phys_id Miscellaneous kernel command line fixes - - - --- 2019-04-10 Atish Patra New
[3/3] RISC-V: Add DEBUG_TLBFLUSH option. TLB flush counters - - - --- 2019-04-10 Atish Patra New
[2/3] RISC-V: Update tlb flush counters TLB flush counters - - - --- 2019-04-10 Atish Patra New
[1/3] x86: Update DEBUG_TLBFLUSH options description. TLB flush counters - 1 - --- 2019-04-10 Atish Patra New
[RFC] RISC-V: Add kexec support [RFC] RISC-V: Add kexec support - - - --- 2019-04-10 Nick Kossifidis New
[RFC,06/41] riscv/stacktrace: Remove the pointless ULONG_MAX marker Untitled series #103625 - - - --- 2019-04-10 Thomas Gleixner New
[v2,2/2] riscv: Introduce huge page support for 32/64bit kernel Hugetlbfs support for riscv - - - --- 2019-04-09 Alexandre Ghiti New
[v2,1/2] x86, arm64: Move ARCH_WANT_HUGE_PMD_SHARE config in arch/Kconfig Hugetlbfs support for riscv - 1 - --- 2019-04-09 Alexandre Ghiti New
[v3] RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems [v3] RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems - 1 - --- 2019-04-05 Anup Patel New
[GIT,PULL] RISC-V Patches for 5.1-rc4 [GIT,PULL] RISC-V Patches for 5.1-rc4 - - - --- 2019-04-04 Palmer Dabbelt New
[v2,5/5] riscv: Make mmap allocation top-down by default Provide generic top-down mmap layout functions - 1 - --- 2019-04-04 Alexandre Ghiti New
[v2,4/5] mips: Use generic mmap top-down layout Provide generic top-down mmap layout functions - - - --- 2019-04-04 Alexandre Ghiti New
[v2,3/5] arm: Use generic mmap top-down layout Provide generic top-down mmap layout functions - - - --- 2019-04-04 Alexandre Ghiti New
[v2,2/5] arm64, mm: Move generic mmap layout functions to mm Provide generic top-down mmap layout functions - - - --- 2019-04-04 Alexandre Ghiti New
[v2,1/5] mm, fs: Move randomize_stack_top from fs to mm Provide generic top-down mmap layout functions - 1 - --- 2019-04-04 Alexandre Ghiti New
dt-bindings: clock: sifive: add FU540-C000 PRCI clock constants dt-bindings: clock: sifive: add FU540-C000 PRCI clock constants - 1 - --- 2019-04-04 Paul Walmsley New
[v8,06/20] riscv: mm: Add p?d_large() definitions Untitled series #100763 - 1 - --- 2019-04-03 Steven Price New
[v2] RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems [v2] RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems - 1 - --- 2019-04-02 Anup Patel New
[3/3] riscv/signal: Fixup additional syscall restarting [1/3] csky: Use in_syscall & forget_syscall instead of r11_sig - 1 - --- 2019-04-02 Guo Ren New
[2/3] csky: Reconstruct signal.c and entry.S [1/3] csky: Use in_syscall & forget_syscall instead of r11_sig - - - --- 2019-04-02 Guo Ren New
[1/3] csky: Use in_syscall & forget_syscall instead of r11_sig [1/3] csky: Use in_syscall & forget_syscall instead of r11_sig - - - --- 2019-04-02 Guo Ren New
RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems - - - --- 2019-04-02 Anup Patel New
[6/6,v3] syscalls: Remove start and number from syscall_set_arguments() args Untitled series #99641 1 2 - --- 2019-04-01 Steven Rostedt New
[5/6,v3] syscalls: Remove start and number from syscall_get_arguments() args Untitled series #99641 2 2 - --- 2019-04-01 Steven Rostedt New
[3/6,v3] riscv: Fix syscall_get_arguments() and syscall_set_arguments() Untitled series #99641 2 - - --- 2019-04-01 Steven Rostedt New
riscv: fix syscall_get_arguments() and syscall_set_arguments() riscv: fix syscall_get_arguments() and syscall_set_arguments() - - - --- 2019-03-29 Dmitry V. Levin New
[v3] RISC-V: Implement ASID allocator [v3] RISC-V: Implement ASID allocator - - - --- 2019-03-29 Anup Patel New
[RFC,4/4,v2] syscalls: Remove start and number from syscall_set_arguments() args Untitled series #98371 - - - --- 2019-03-28 Steven Rostedt New
[RFC,3/4,v2] syscalls: Remove start and number from syscall_get_arguments() args Untitled series #98371 - - - --- 2019-03-28 Steven Rostedt New
[v7,06/20] riscv: mm: Add p?d_large() definitions Untitled series #98127 - - - --- 2019-03-28 Steven Price New
[v2] RISC-V: Implement ASID allocator [v2] RISC-V: Implement ASID allocator - - - --- 2019-03-28 Anup Patel New
[7/7] RISC-V: Implement pte_devmap() RISC-V: Sparsmem, Memory Hotplug and pte_devmap for P2P - - - --- 2019-03-27 Logan Gunthorpe New
[6/7] RISC-V: Implement memory hot remove RISC-V: Sparsmem, Memory Hotplug and pte_devmap for P2P - - - --- 2019-03-27 Logan Gunthorpe New
[5/7] RISC-V: Implement memory hotplug RISC-V: Sparsmem, Memory Hotplug and pte_devmap for P2P - - - --- 2019-03-27 Logan Gunthorpe New
[4/7] RISC-V: Update page tables to cover the whole linear mapping RISC-V: Sparsmem, Memory Hotplug and pte_devmap for P2P - - - --- 2019-03-27 Logan Gunthorpe New
[3/7] RISC-V: Rework kernel's virtual address space mapping RISC-V: Sparsmem, Memory Hotplug and pte_devmap for P2P - - - --- 2019-03-27 Logan Gunthorpe New
[2/7] RISC-V: doc: Add file describing the virtual memory map RISC-V: Sparsmem, Memory Hotplug and pte_devmap for P2P - - - --- 2019-03-27 Logan Gunthorpe New
[1/7] RISC-V: Implement sparsemem RISC-V: Sparsmem, Memory Hotplug and pte_devmap for P2P - 2 - --- 2019-03-27 Logan Gunthorpe New
RISC-V: Implement ASID allocator RISC-V: Implement ASID allocator - - - --- 2019-03-27 Anup Patel New
[v4,5/5] riscv: implement IPI-based remote TLB shootdown TLB/I$ flush cleanups and improvements - - 1 --- 2019-03-27 Gary Guo New
[v4,3/5] riscv: fix sbi_remote_sfence_vma{,_asid}. TLB/I$ flush cleanups and improvements - 2 - --- 2019-03-27 Gary Guo New
[v4,4/5] riscv: rewrite tlb flush for performance TLB/I$ flush cleanups and improvements - - 1 --- 2019-03-27 Gary Guo New
[v4,2/5] riscv: move switch_mm to its own file TLB/I$ flush cleanups and improvements - 2 - --- 2019-03-27 Gary Guo New
[v4,1/5] riscv: move flush_icache_{all,mm} to cacheflush.c TLB/I$ flush cleanups and improvements - 2 - --- 2019-03-27 Gary Guo New
[v6,05/19] riscv: mm: Add p?d_large() definitions Untitled series #97097 - - - --- 2019-03-26 Steven Price New
[v4] RISC-V: Always compile mm/init.c with cmodel=medany and notrace [v4] RISC-V: Always compile mm/init.c with cmodel=medany and notrace - 2 - --- 2019-03-26 Anup Patel New
[v11,2/2] pwm: sifive: Add a driver for SiFive SoC PWM PWM support for HiFive Unleashed - - - --- 2019-03-25 Yash Shah New
[v11,1/2] pwm: sifive: Add DT documentation for SiFive PWM Controller PWM support for HiFive Unleashed - 1 - --- 2019-03-25 Yash Shah New
[v3,4/4] RISC-V: Allow booting kernel from any 4KB aligned address Boot RISC-V kernel from any 4KB aligned address - - - --- 2019-03-25 Anup Patel New
[v3,3/4] RISC-V: Remove redundant trampoline page table Boot RISC-V kernel from any 4KB aligned address - 1 - --- 2019-03-25 Anup Patel New
[v3,2/4] RISC-V: Fix memory reservation in setup_bootmem() Boot RISC-V kernel from any 4KB aligned address - 2 - --- 2019-03-25 Anup Patel New
[v3,1/4] RISC-V: Add separate defconfig for 32bit systems Boot RISC-V kernel from any 4KB aligned address - - - --- 2019-03-25 Anup Patel New
[v3] RISC-V: Always compile mm/init.c with cmodel=medany and notrace [v3] RISC-V: Always compile mm/init.c with cmodel=medany and notrace - 2 - --- 2019-03-25 Anup Patel New
[v2] RISC-V: Always compile mm/init.c with cmodel=medany [v2] RISC-V: Always compile mm/init.c with cmodel=medany - 1 - --- 2019-03-25 Anup Patel New
RISC-V: Always compile mm/init.c with cmodel=medany RISC-V: Always compile mm/init.c with cmodel=medany - - - --- 2019-03-24 Anup Patel New
clocksource/drivers/riscv: Fix clocksource mask clocksource/drivers/riscv: Fix clocksource mask - 1 - --- 2019-03-22 Atish Patra New
[v5,3/3] locking/rwsem: Optimize down_read_trylock() locking/rwsem: Rwsem rearchitecture part 0 - - - --- 2019-03-22 Waiman Long New
[v5,2/3] locking/rwsem: Remove rwsem-spinlock.c & use rwsem-xadd.c for all archs locking/rwsem: Rwsem rearchitecture part 0 - - - --- 2019-03-22 Waiman Long New
[v5,1/3] locking/rwsem: Remove arch specific rwsem files locking/rwsem: Rwsem rearchitecture part 0 - - - --- 2019-03-22 Waiman Long New
RISC-V: Fix FIXMAP_TOP to avoid overlap with VMALLOC area RISC-V: Fix FIXMAP_TOP to avoid overlap with VMALLOC area - 1 - --- 2019-03-22 Anup Patel New
[4/4] riscv: Make mmap allocation top-down by default Provide generic top-down mmap layout functions - - - --- 2019-03-22 Alexandre Ghiti New
[3/4] mips: Use generic mmap top-down layout Provide generic top-down mmap layout functions - - - --- 2019-03-22 Alexandre Ghiti New
[2/4] arm: Use generic mmap top-down layout Provide generic top-down mmap layout functions - - - --- 2019-03-22 Alexandre Ghiti New
[1/4] arm64, mm: Move generic mmap layout functions to mm Provide generic top-down mmap layout functions - - - --- 2019-03-22 Alexandre Ghiti New
riscv: fix accessing 8-byte variable from RV32 riscv: fix accessing 8-byte variable from RV32 - 1 - --- 2019-03-22 Alan Kao New
[v5,05/19] riscv: mm: Add p?d_large() definitions Untitled series #94885 - - - --- 2019-03-21 Steven Price New
[v2,5/5] RISC-V: Fix memory reservation in setup_bootmem() Boot RISC-V kernel from any 4KB aligned address - 1 - --- 2019-03-21 Anup Patel New
[v2,4/5] RISC-V: Remove redundant trampoline page table Boot RISC-V kernel from any 4KB aligned address - - - --- 2019-03-21 Anup Patel New
[v2,3/5] RISC-V: Allow booting kernel from any 4KB aligned address Boot RISC-V kernel from any 4KB aligned address - - - --- 2019-03-21 Anup Patel New
[v2,2/5] RISC-V: Make setup_vm() independent of GCC code model Boot RISC-V kernel from any 4KB aligned address - - - --- 2019-03-21 Anup Patel New
[v2,1/5] RISC-V: Add separate defconfig for 32bit systems Boot RISC-V kernel from any 4KB aligned address - - - --- 2019-03-21 Anup Patel New
[RFT/RFC,v3,5/5] RISC-V: Parse cpu topology during boot. Unify CPU topology across ARM & RISC-V - - - --- 2019-03-20 Atish Patra New
[RFT/RFC,v3,4/5] arm: Use common cpu_topology Unify CPU topology across ARM & RISC-V - - - --- 2019-03-20 Atish Patra New
[RFT/RFC,v3,3/5] cpu-topology: Move cpu topology code to common code. Unify CPU topology across ARM & RISC-V - - 1 --- 2019-03-20 Atish Patra New
[RFT/RFC,v3,2/5] dt-binding: cpu-topology: Move cpu-map to a common binding. Unify CPU topology across ARM & RISC-V - 2 - --- 2019-03-20 Atish Patra New
[RFT/RFC,v3,1/5] Documentation: DT: arm: add support for sockets defining package boundaries Unify CPU topology across ARM & RISC-V - 1 - --- 2019-03-20 Atish Patra New
irqchip: plic: Fix priority base offset irqchip: plic: Fix priority base offset - - - --- 2019-03-20 Alistair Francis New
[2/2] edac: sifive: Add EDAC driver for SiFive FU540-C000 chip EDAC Support for SiFive SoCs - - - --- 2019-03-20 Yash Shah New
[1/2] edac: sifive: Add DT documentation for SiFive EDAC driver and subcomponent EDAC Support for SiFive SoCs - - - --- 2019-03-20 Yash Shah New
[RFT/RFC,v2,4/4] RISC-V: Parse cpu topology during boot. Unify CPU topology across ARM & RISC-V - - - --- 2019-03-20 Atish Patra New
[RFT/RFC,v2,3/4] arm: Use common cpu_topology Unify CPU topology across ARM & RISC-V - - - --- 2019-03-20 Atish Patra New
[RFT/RFC,v2,2/4] cpu-topology: Move cpu topology code to common code. Untitled series #94029 - - 1 --- 2019-03-20 Atish Patra New
[RFT/RFC,v2,1/4] dt-binding: cpu-topology: Move cpu-map to a common binding. Unify CPU topology across ARM & RISC-V - 1 - --- 2019-03-20 Atish Patra New
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