| Message ID | 032c06642b01f06c86ba8bcd2108d18c005b57eb.1713258948.git.unicorn_wang@outlook.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | mmc: sdhci-of-dwcmshc: support Sophgo SG2042 | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
On Tue, Apr 16, 2024 at 05:50:37PM +0800, Chen Wang wrote: > From: Chen Wang <unicorn_wang@outlook.com> > > SG2042 use Synopsys dwcnshc IP for SD/eMMC controllers. > > SG2042 defines 3 clocks for SD/eMMC controllers. > - AXI_EMMC/AXI_SD for aclk/hclk(Bus interface clocks in DWC_mshc) > and blck(Core Base Clock in DWC_mshc), these 3 clocks share one > source, so reuse existing "core". > - 100K_EMMC/100K_SD for cqetmclk(Timer clocks in DWC_mshc), so reuse > existing "timer" which was added for rockchip specified. > - EMMC_100M/SD_100M for cclk(Card clocks in DWC_mshc), add new "card". > > Adding some examples. > > Signed-off-by: Chen Wang <unicorn_wang@outlook.com> > --- > .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 67 ++++++++++++++----- > 1 file changed, 51 insertions(+), 16 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml > index 4d3031d9965f..a04ccae216cf 100644 > --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml > +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml > @@ -21,6 +21,7 @@ properties: > - snps,dwcmshc-sdhci > - sophgo,cv1800b-dwcmshc > - sophgo,sg2002-dwcmshc > + - sophgo,sg2042-dwcmshc > - thead,th1520-dwcmshc > > reg: > @@ -30,23 +31,36 @@ properties: > maxItems: 1 > > clocks: > - minItems: 1 > - items: > - - description: core clock > - - description: bus clock for optional > - - description: axi clock for rockchip specified > - - description: block clock for rockchip specified > - - description: timer clock for rockchip specified > - > + anyOf: > + - minItems: 1 > + items: > + - description: core clock > + - description: bus clock for optional > + - description: axi clock for rockchip specified > + - description: block clock for rockchip specified > + - description: timer clock for rockchip specified > + > + - minItems: 1 I don't think this minItems is needed, this is for one device which has all 3, no? I also think this combination should only be permitted for the sg2042, since it is not valid for the existing devices. Cheers, Conor. > + items: > + - description: core clock > + - description: timer clock > + - description: card clock > > clock-names: > - minItems: 1 > - items: > - - const: core > - - const: bus > - - const: axi > - - const: block > - - const: timer > + anyOf: > + - minItems: 1 > + items: > + - const: core > + - const: bus > + - const: axi > + - const: block > + - const: timer > + > + - minItems: 1 > + items: > + - const: core > + - const: timer > + - const: card > > resets: > maxItems: 5 > @@ -96,5 +110,26 @@ examples: > #address-cells = <1>; > #size-cells = <0>; > }; > - > + - | > + mmc@bb0000 { > + compatible = "snps,dwcmshc-sdhci"; > + reg = <0xbb000 0x1000>; > + interrupts = <0 25 0x4>; > + clocks = <&cru 17>; > + clock-names = "core"; > + bus-width = <8>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + - | > + mmc@cc0000 { > + compatible = "snps,dwcmshc-sdhci"; > + reg = <0xcc000 0x1000>; > + interrupts = <0 25 0x4>; > + clocks = <&cru 17>, <&cru 18>, <&cru 19>; > + clock-names = "core", "timer", "card"; > + bus-width = <8>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > ... > -- > 2.25.1 >
On 2024/4/17 0:44, Conor Dooley wrote: > On Tue, Apr 16, 2024 at 05:50:37PM +0800, Chen Wang wrote: [......] >> + anyOf: >> + - minItems: 1 >> + items: >> + - description: core clock >> + - description: bus clock for optional >> + - description: axi clock for rockchip specified >> + - description: block clock for rockchip specified >> + - description: timer clock for rockchip specified >> + >> + - minItems: 1 > I don't think this minItems is needed, this is for one device which has > all 3, no? Yes, SG2042 requires all the 3 clocks presented, I will remove this minItems. > I also think this combination should only be permitted for the sg2042, > since it is not valid for the existing devices. Yes, I will add condition to allow this combination only for sg2042, thanks. > Cheers, > Conor. [......]
diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index 4d3031d9965f..a04ccae216cf 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -21,6 +21,7 @@ properties: - snps,dwcmshc-sdhci - sophgo,cv1800b-dwcmshc - sophgo,sg2002-dwcmshc + - sophgo,sg2042-dwcmshc - thead,th1520-dwcmshc reg: @@ -30,23 +31,36 @@ properties: maxItems: 1 clocks: - minItems: 1 - items: - - description: core clock - - description: bus clock for optional - - description: axi clock for rockchip specified - - description: block clock for rockchip specified - - description: timer clock for rockchip specified - + anyOf: + - minItems: 1 + items: + - description: core clock + - description: bus clock for optional + - description: axi clock for rockchip specified + - description: block clock for rockchip specified + - description: timer clock for rockchip specified + + - minItems: 1 + items: + - description: core clock + - description: timer clock + - description: card clock clock-names: - minItems: 1 - items: - - const: core - - const: bus - - const: axi - - const: block - - const: timer + anyOf: + - minItems: 1 + items: + - const: core + - const: bus + - const: axi + - const: block + - const: timer + + - minItems: 1 + items: + - const: core + - const: timer + - const: card resets: maxItems: 5 @@ -96,5 +110,26 @@ examples: #address-cells = <1>; #size-cells = <0>; }; - + - | + mmc@bb0000 { + compatible = "snps,dwcmshc-sdhci"; + reg = <0xbb000 0x1000>; + interrupts = <0 25 0x4>; + clocks = <&cru 17>; + clock-names = "core"; + bus-width = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; + - | + mmc@cc0000 { + compatible = "snps,dwcmshc-sdhci"; + reg = <0xcc000 0x1000>; + interrupts = <0 25 0x4>; + clocks = <&cru 17>, <&cru 18>, <&cru 19>; + clock-names = "core", "timer", "card"; + bus-width = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; ...