| Message ID | 1561375453-3135-1-git-send-email-yash.shah@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: dts: Re-organize SPI DT nodes | expand |
On Mon, 24 Jun 2019, Yash Shah wrote: > As per the General convention, define only device DT node in SOC DTSi > file with status = "disabled" and enable device in Board DTS file with > status = "okay" > > Reported-by: Anup Patel <anup@brainfault.org> > Signed-off-by: Yash Shah <yash.shah@sifive.com> This is a good start, but should also cover the other I/O devices in the chip DT file. The mandatory internal devices, like the PRCI and PLIC, can stay the way they are. - Paul
On Tue, Jun 25, 2019 at 2:53 AM Paul Walmsley <paul.walmsley@sifive.com> wrote: > > On Mon, 24 Jun 2019, Yash Shah wrote: > > > As per the General convention, define only device DT node in SOC DTSi > > file with status = "disabled" and enable device in Board DTS file with > > status = "okay" > > > > Reported-by: Anup Patel <anup@brainfault.org> > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > This is a good start, but should also cover the other I/O devices in the > chip DT file. The mandatory internal devices, like the PRCI and PLIC, can > stay the way they are. Yes, this convention only applies to SoC devices with external connections so PRCI, PLIC, and CLINT DT nodes are not required to follow this. Eventually, this convention helps when we have multiple boards of same SOC and each board having different set of peripherals connections. Regards, Anup
On Tue, Jun 25, 2019 at 2:53 AM Paul Walmsley <paul.walmsley@sifive.com> wrote: > > On Mon, 24 Jun 2019, Yash Shah wrote: > > > As per the General convention, define only device DT node in SOC DTSi > > file with status = "disabled" and enable device in Board DTS file with > > status = "okay" > > > > Reported-by: Anup Patel <anup@brainfault.org> > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > This is a good start, but should also cover the other I/O devices in the > chip DT file. The mandatory internal devices, like the PRCI and PLIC, can > stay the way they are. Ok, I will send another patch which will cover the other I/O devices as well. Please ignore this patch. - Yash > > > - Paul
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 4e8fbde..270f6e8 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -203,6 +203,7 @@ interrupt-parent = <&plic0>; interrupts = <51>; clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; @@ -213,6 +214,7 @@ interrupt-parent = <&plic0>; interrupts = <52>; clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; @@ -222,6 +224,7 @@ interrupt-parent = <&plic0>; interrupts = <6>; clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts index 4da8870..73e2af6 100644 --- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts @@ -43,6 +43,7 @@ }; &qspi0 { + status = "okay"; flash@0 { compatible = "issi,is25wp256", "jedec,spi-nor"; reg = <0>;
As per the General convention, define only device DT node in SOC DTSi file with status = "disabled" and enable device in Board DTS file with status = "okay" Reported-by: Anup Patel <anup@brainfault.org> Signed-off-by: Yash Shah <yash.shah@sifive.com> --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 3 +++ arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 1 + 2 files changed, 4 insertions(+)