Message ID | 1578897500-23897-2-git-send-email-yash.shah@sifive.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | cacheinfo support to read no. of L2 cache ways enabled | expand |
On Mon, Jan 13, 2020 at 12:09 PM Yash Shah <yash.shah@sifive.com> wrote: > > Implement cache_get_priv_group() that will make use of a generic ops > structure to return a private attribute group for custom cache info. > > Using riscv_set_cacheinfo_ops() users can hook their own custom function > to return the private attribute group for cacheinfo. In future we can > add more ops to this generic ops structure for SOC specific cacheinfo. > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > --- > arch/riscv/include/asm/cacheinfo.h | 15 +++++++++++++++ > arch/riscv/kernel/cacheinfo.c | 17 +++++++++++++++++ > 2 files changed, 32 insertions(+) > create mode 100644 arch/riscv/include/asm/cacheinfo.h > > diff --git a/arch/riscv/include/asm/cacheinfo.h b/arch/riscv/include/asm/cacheinfo.h > new file mode 100644 > index 0000000..5d9662e > --- /dev/null > +++ b/arch/riscv/include/asm/cacheinfo.h > @@ -0,0 +1,15 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > + > +#ifndef _ASM_RISCV_CACHEINFO_H > +#define _ASM_RISCV_CACHEINFO_H > + > +#include <linux/cacheinfo.h> > + > +struct riscv_cacheinfo_ops { > + const struct attribute_group * (*get_priv_group)(struct cacheinfo > + *this_leaf); > +}; > + > +void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops); > + > +#endif /* _ASM_RISCV_CACHEINFO_H */ > diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c > index 4c90c07..bd0f122 100644 > --- a/arch/riscv/kernel/cacheinfo.c > +++ b/arch/riscv/kernel/cacheinfo.c > @@ -7,6 +7,23 @@ > #include <linux/cpu.h> > #include <linux/of.h> > #include <linux/of_device.h> > +#include <asm/cacheinfo.h> > + > +static struct riscv_cacheinfo_ops *rv_cache_ops; > + > +void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops) > +{ > + rv_cache_ops = ops; > +} > +EXPORT_SYMBOL_GPL(riscv_set_cacheinfo_ops); > + > +const struct attribute_group * > +cache_get_priv_group(struct cacheinfo *this_leaf) > +{ > + if (rv_cache_ops && rv_cache_ops->get_priv_group) > + return rv_cache_ops->get_priv_group(this_leaf); > + return NULL; > +} > > static void ci_leaf_init(struct cacheinfo *this_leaf, > struct device_node *node, > -- > 2.7.4 > LGTM. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup
diff --git a/arch/riscv/include/asm/cacheinfo.h b/arch/riscv/include/asm/cacheinfo.h new file mode 100644 index 0000000..5d9662e --- /dev/null +++ b/arch/riscv/include/asm/cacheinfo.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_RISCV_CACHEINFO_H +#define _ASM_RISCV_CACHEINFO_H + +#include <linux/cacheinfo.h> + +struct riscv_cacheinfo_ops { + const struct attribute_group * (*get_priv_group)(struct cacheinfo + *this_leaf); +}; + +void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops); + +#endif /* _ASM_RISCV_CACHEINFO_H */ diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c index 4c90c07..bd0f122 100644 --- a/arch/riscv/kernel/cacheinfo.c +++ b/arch/riscv/kernel/cacheinfo.c @@ -7,6 +7,23 @@ #include <linux/cpu.h> #include <linux/of.h> #include <linux/of_device.h> +#include <asm/cacheinfo.h> + +static struct riscv_cacheinfo_ops *rv_cache_ops; + +void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops) +{ + rv_cache_ops = ops; +} +EXPORT_SYMBOL_GPL(riscv_set_cacheinfo_ops); + +const struct attribute_group * +cache_get_priv_group(struct cacheinfo *this_leaf) +{ + if (rv_cache_ops && rv_cache_ops->get_priv_group) + return rv_cache_ops->get_priv_group(this_leaf); + return NULL; +} static void ci_leaf_init(struct cacheinfo *this_leaf, struct device_node *node,
Implement cache_get_priv_group() that will make use of a generic ops structure to return a private attribute group for custom cache info. Using riscv_set_cacheinfo_ops() users can hook their own custom function to return the private attribute group for cacheinfo. In future we can add more ops to this generic ops structure for SOC specific cacheinfo. Signed-off-by: Yash Shah <yash.shah@sifive.com> --- arch/riscv/include/asm/cacheinfo.h | 15 +++++++++++++++ arch/riscv/kernel/cacheinfo.c | 17 +++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/riscv/include/asm/cacheinfo.h