Message ID | 1589885187-31247-2-git-send-email-sagar.kadam@sifive.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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dkim=none (message not signed) header.d=none;lists.infradead.org; dmarc=none action=none header.from=sifive.com; Received: from DM6PR13MB2619.namprd13.prod.outlook.com (2603:10b6:5:140::13) by DM6PR13MB3882.namprd13.prod.outlook.com (2603:10b6:5:22a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3000.11; Tue, 19 May 2020 10:46:47 +0000 Received: from DM6PR13MB2619.namprd13.prod.outlook.com ([fe80::ad23:dfbe:7ec:e5ca]) by DM6PR13MB2619.namprd13.prod.outlook.com ([fe80::ad23:dfbe:7ec:e5ca%3]) with mapi id 15.20.3000.015; Tue, 19 May 2020 10:46:47 +0000 From: Sagar Shrikant Kadam <sagar.kadam@sifive.com> To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org Subject: [PATCH v2 1/2] riscv: defconfig: enable spi nor on Hifive Unleashed A00 Date: Tue, 19 May 2020 03:46:26 -0700 Message-Id: <1589885187-31247-2-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589885187-31247-1-git-send-email-sagar.kadam@sifive.com> References: <1589885187-31247-1-git-send-email-sagar.kadam@sifive.com> Content-Type: text/plain X-ClientProxiedBy: BYAPR05CA0073.namprd05.prod.outlook.com (2603:10b6:a03:e0::14) To DM6PR13MB2619.namprd13.prod.outlook.com (2603:10b6:5:140::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from gamma07.internal.sifive.com (64.62.193.194) by BYAPR05CA0073.namprd05.prod.outlook.com (2603:10b6:a03:e0::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3021.10 via Frontend Transport; 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enable spi flash and update is25wp256d page write capabilities
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expand
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diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 216286d..bcb0b1a 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -7,6 +7,7 @@ config SOC_SIFIVE select CLK_SIFIVE select CLK_SIFIVE_FU540_PRCI select SIFIVE_PLIC + imply SPI_SIFIVE if SPI help This enables support for SiFive SoC platform hardware. diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 4da4886..8e2d467 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -62,7 +62,6 @@ CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y CONFIG_SPI=y -CONFIG_SPI_SIFIVE=y # CONFIG_PTP_1588_CLOCK is not set CONFIG_POWER_RESET=y CONFIG_DRM=y @@ -80,6 +79,8 @@ CONFIG_USB_STORAGE=y CONFIG_USB_UAS=y CONFIG_MMC=y CONFIG_MMC_SPI=y +CONFIG_MTD=y +CONFIG_MTD_SPI_NOR=y CONFIG_RTC_CLASS=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_BALLOON=y
Enable MTD based SPI-NOR framework in order to use spi flash available on HiFive Unleashed A00 board, and move SPI_SIFIVE to Kconfig.socs. The configurability of SPI_SIFIVE is retained and still can be enabled or disabled as required. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> --- arch/riscv/Kconfig.socs | 1 + arch/riscv/configs/defconfig | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-)