[11/17] riscv: read hart ID from mhartid on boot

Message ID	20190610221621.10938-12-hch@lst.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org> From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com> Subject: [PATCH 11/17] riscv: read hart ID from mhartid on boot Date: Tue, 11 Jun 2019 00:16:15 +0200 Message-Id: <20190610221621.10938-12-hch@lst.de> In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 Precedence: list Cc: linux-mm@kvack.org, Damien Le Moal <damien.lemoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, uclinux-dev@uclinux.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org
Series	[01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU \| expand [01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU [02/17] mm: stub out all of swapops.h for !CONFIG_MMU [03/17] mm/nommu: fix the MAP_UNINITIALIZED flag [04/17] irqchip/sifive-plic: set max threshold for ignored handlers [05/17] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm [06/17] riscv: clear the instruction cache and all registers when booting [07/17] riscv: refactor the IPI code [08/17] riscv: abstract out CSR names for supervisor vs machine mode [09/17] riscv: improve the default power off implementation [10/17] riscv: provide a flat entry loader [11/17] riscv: read hart ID from mhartid on boot [12/17] riscv: provide native clint access for M-mode [13/17] riscv: implement remote sfence.i natively for M-mode [14/17] riscv: poison SBI calls for M-mode [15/17] riscv: don't allow selecting SBI-based drivers for M-mode [16/17] riscv: use the correct interrupt levels for M-mode [17/17] riscv: add nommu support

Message ID

20190610221621.10938-12-hch@lst.de (mailing list archive)

State

New, archived

Headers

From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>
Subject: [PATCH 11/17] riscv: read hart ID from mhartid on boot
Date: Tue, 11 Jun 2019 00:16:15 +0200
Message-Id: <20190610221621.10938-12-hch@lst.de>
In-Reply-To: <20190610221621.10938-1-hch@lst.de>
References: <20190610221621.10938-1-hch@lst.de>
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Cc: linux-mm@kvack.org, Damien Le Moal <damien.lemoal@wdc.com>,
 linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
 uclinux-dev@uclinux.org
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Series

[01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU | expand

Commit Message

Christoph Hellwig June 10, 2019, 10:16 p.m. UTC

From: Damien Le Moal <damien.lemoal@wdc.com>

When in M-Mode, we can use the mhartid CSR to get the ID of the running
HART. Doing so, direct M-Mode boot without firmware is possible.

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
---
 arch/riscv/kernel/head.S | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index cb5691d82b0b..e05379fd8b64 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -25,6 +25,14 @@  ENTRY(_start)
 	/* Reset all registers except ra, a0,a1 */
 	call reset_regs
 
+#ifdef CONFIG_M_MODE
+	/*
+	 * The hartid in a0 is expected later on, and we have no firmware
+	 * to hand it to us.
+	 */
+	csrr a0, mhartid
+#endif
+
 	/* Load the global pointer */
 .option push
 .option norelax

[11/17] riscv: read hart ID from mhartid on boot

Commit Message

Patch