[10/17] riscv: read the hart ID from mhartid on boot

Message ID	20190624054311.30256-11-hch@lst.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org> From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Subject: [PATCH 10/17] riscv: read the hart ID from mhartid on boot Date: Mon, 24 Jun 2019 07:43:04 +0200 Message-Id: <20190624054311.30256-11-hch@lst.de> In-Reply-To: <20190624054311.30256-1-hch@lst.de> References: <20190624054311.30256-1-hch@lst.de> MIME-Version: 1.0 Precedence: list Cc: linux-mm@kvack.org, Damien Le Moal <Damien.LeMoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org
Series	[01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU \| expand [01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU [02/17] mm: stub out all of swapops.h for !CONFIG_MMU [03/17] mm/nommu: fix the MAP_UNINITIALIZED flag [04/17] irqchip/sifive-plic: set max threshold for ignored handlers [05/17] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm [06/17] riscv: refactor the IPI code [07/17] riscv: abstract out CSR names for supervisor vs machine mode [08/17] riscv: improve the default power off implementation [09/17] riscv: provide a flat entry loader [10/17] riscv: read the hart ID from mhartid on boot [11/17] riscv: provide native clint access for M-mode [12/17] riscv: implement remote sfence.i natively for M-mode [13/17] riscv: poison SBI calls for M-mode [14/17] riscv: don't allow selecting SBI-based drivers for M-mode [15/17] riscv: use the correct interrupt levels for M-mode [16/17] riscv: clear the instruction cache and all registers when booting [17/17] riscv: add nommu support

Message ID

20190624054311.30256-11-hch@lst.de (mailing list archive)

State

New, archived

Headers

From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
 Paul Walmsley <paul.walmsley@sifive.com>
Subject: [PATCH 10/17] riscv: read the hart ID from mhartid on boot
Date: Mon, 24 Jun 2019 07:43:04 +0200
Message-Id: <20190624054311.30256-11-hch@lst.de>
In-Reply-To: <20190624054311.30256-1-hch@lst.de>
References: <20190624054311.30256-1-hch@lst.de>
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Cc: linux-mm@kvack.org, Damien Le Moal <Damien.LeMoal@wdc.com>,
 linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
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Series

[01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU | expand

Commit Message

Christoph Hellwig June 24, 2019, 5:43 a.m. UTC

From: Damien Le Moal <Damien.LeMoal@wdc.com>

When in M-Mode, we can use the mhartid CSR to get the ID of the running
HART. Doing so, direct M-Mode boot without firmware is possible.

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/riscv/kernel/head.S | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Atish Patra July 1, 2019, 9:15 p.m. UTC | #1

On Mon, 2019-06-24 at 07:43 +0200, Christoph Hellwig wrote:
> From: Damien Le Moal <Damien.LeMoal@wdc.com>
> 
> When in M-Mode, we can use the mhartid CSR to get the ID of the
> running
> HART. Doing so, direct M-Mode boot without firmware is possible.
> 
> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
>  arch/riscv/kernel/head.S | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index e5fa5481aa99..a4c170e41a34 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -18,6 +18,14 @@ ENTRY(_start)
>  	csrw CSR_XIE, zero
>  	csrw CSR_XIP, zero
>  
> +#ifdef CONFIG_M_MODE
> +	/*
> +	 * The hartid in a0 is expected later on, and we have no
> firmware
> +	 * to hand it to us.
> +	 */
> +	csrr a0, mhartid

I think you should add SR_MHARTID and use that instead of direct csr
name.
The following patch replaced all occurrence of csr name usage from
kernel with CSR numbers.

https://patchwork.kernel.org/patch/10916293/

With that change, 

Reviewed-by: Atish Patra <atish.patra@wdc.com>

> +#endif
> +
>  	/* Load the global pointer */
>  .option push
>  .option norelax

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index e5fa5481aa99..a4c170e41a34 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -18,6 +18,14 @@  ENTRY(_start)
 	csrw CSR_XIE, zero
 	csrw CSR_XIP, zero
 
+#ifdef CONFIG_M_MODE
+	/*
+	 * The hartid in a0 is expected later on, and we have no firmware
+	 * to hand it to us.
+	 */
+	csrr a0, mhartid
+#endif
+
 	/* Load the global pointer */
 .option push
 .option norelax

[10/17] riscv: read the hart ID from mhartid on boot

Commit Message

Comments

Patch