| Message ID | 20190803042723.7163-3-atish.patra@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Miscellaneous fixes | expand |
Hi Anup, Atish, On Fri, 2 Aug 2019, Atish Patra wrote: > From: Anup Patel <anup.patel@wdc.com> > > This patch adds riscv_isa integer to represent ISA features common > across all CPUs. The riscv_isa is not same as elf_hwcap because > elf_hwcap will only have ISA features relevant for user-space apps > whereas riscv_isa will have ISA features relevant to both kernel > and user-space apps. > > One of the use case is KVM hypervisor where riscv_isa will be used > to do following operations: > > 1. Check whether hypervisor extension is available > 2. Find ISA features that need to be virtualized (e.g. floating > point support, vector extension, etc.) > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > Signed-off-by: Atish Patra <atish.patra@wdc.com> Do you have any opinions on how this patch might change for the Z-prefix extensions? This bitfield approach probably won't scale, and with the EXPORT_SYMBOL(), it might be worth trying to put together a approach that would work over the long term? - Paul
On Wed, Aug 7, 2019 at 3:24 AM Paul Walmsley <paul.walmsley@sifive.com> wrote: > > Hi Anup, Atish, > > On Fri, 2 Aug 2019, Atish Patra wrote: > > > From: Anup Patel <anup.patel@wdc.com> > > > > This patch adds riscv_isa integer to represent ISA features common > > across all CPUs. The riscv_isa is not same as elf_hwcap because > > elf_hwcap will only have ISA features relevant for user-space apps > > whereas riscv_isa will have ISA features relevant to both kernel > > and user-space apps. > > > > One of the use case is KVM hypervisor where riscv_isa will be used > > to do following operations: > > > > 1. Check whether hypervisor extension is available > > 2. Find ISA features that need to be virtualized (e.g. floating > > point support, vector extension, etc.) > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > > Do you have any opinions on how this patch might change for the Z-prefix > extensions? This bitfield approach probably won't scale, and with the > EXPORT_SYMBOL(), it might be worth trying to put together a approach that > would work over the long term? Our plan is to use bitmap instead of bitfield and all Zxyz extensions will be assigned bit positions "27 + i" where "i" will be based on order in-which they are defined in RISC-V spec. In general, "i" is just a unique relative index (starting from 0). To summarize, the existing bitfield approach can be naturally extended using bitmap. We will update this patch accordingly. Regards, Anup
On Fri, Aug 02, 2019 at 09:27:21PM -0700, Atish Patra wrote: > From: Anup Patel <anup.patel@wdc.com> > > This patch adds riscv_isa integer to represent ISA features common > across all CPUs. The riscv_isa is not same as elf_hwcap because > elf_hwcap will only have ISA features relevant for user-space apps > whereas riscv_isa will have ISA features relevant to both kernel > and user-space apps. > > One of the use case is KVM hypervisor where riscv_isa will be used > to do following operations: Please add this to the kvm series. Right now this is just dead code.
On Wed, Aug 7, 2019 at 12:21 PM Christoph Hellwig <hch@infradead.org> wrote: > > On Fri, Aug 02, 2019 at 09:27:21PM -0700, Atish Patra wrote: > > From: Anup Patel <anup.patel@wdc.com> > > > > This patch adds riscv_isa integer to represent ISA features common > > across all CPUs. The riscv_isa is not same as elf_hwcap because > > elf_hwcap will only have ISA features relevant for user-space apps > > whereas riscv_isa will have ISA features relevant to both kernel > > and user-space apps. > > > > One of the use case is KVM hypervisor where riscv_isa will be used > > to do following operations: > > Please add this to the kvm series. Right now this is just dead code. Sure, I will include this patch in KVM series. Regards, Anup
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 7ecb7c6a57b1..717306780add 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -22,5 +22,21 @@ enum { }; extern unsigned long elf_hwcap; + +#define RISCV_ISA_EXT_a (1UL << ('a' - 'a')) +#define RISCV_ISA_EXT_c (1UL << ('c' - 'a')) +#define RISCV_ISA_EXT_d (1UL << ('d' - 'a')) +#define RISCV_ISA_EXT_f (1UL << ('f' - 'a')) +#define RISCV_ISA_EXT_h (1UL << ('h' - 'a')) +#define RISCV_ISA_EXT_i (1UL << ('i' - 'a')) +#define RISCV_ISA_EXT_m (1UL << ('m' - 'a')) +#define RISCV_ISA_EXT_s (1UL << ('s' - 'a')) +#define RISCV_ISA_EXT_u (1UL << ('u' - 'a')) + +extern unsigned long riscv_isa; + +#define riscv_isa_extension_available(ext_char) \ + (riscv_isa & RISCV_ISA_EXT_##ext_char) + #endif #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b1ade9a49347..becc99272341 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -12,6 +12,9 @@ #include <asm/smp.h> unsigned long elf_hwcap __read_mostly; +unsigned long riscv_isa __read_mostly; +EXPORT_SYMBOL_GPL(riscv_isa); + #ifdef CONFIG_FPU bool has_fpu __read_mostly; #endif @@ -20,7 +23,8 @@ void riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - size_t i; + char print_str[BITS_PER_LONG+1]; + size_t i, j, isa_len; static unsigned long isa2hwcap[256] = {0}; isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; @@ -31,9 +35,11 @@ void riscv_fill_hwcap(void) isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C; elf_hwcap = 0; + riscv_isa = 0; for_each_of_cpu_node(node) { unsigned long this_hwcap = 0; + unsigned long this_isa = 0; if (riscv_of_processor_hartid(node) < 0) continue; @@ -43,8 +49,20 @@ void riscv_fill_hwcap(void) continue; } - for (i = 0; i < strlen(isa); ++i) + i = 0; + isa_len = strlen(isa); +#if defined(CONFIG_32BIT) + if (!strncmp(isa, "rv32", 4)) + i += 4; +#elif defined(CONFIG_64BIT) + if (!strncmp(isa, "rv64", 4)) + i += 4; +#endif + for (; i < isa_len; ++i) { this_hwcap |= isa2hwcap[(unsigned char)(isa[i])]; + if ('a' <= isa[i] && isa[i] <= 'z') + this_isa |= (1UL << (isa[i] - 'a')); + } /* * All "okay" hart should have same isa. Set HWCAP based on @@ -55,6 +73,11 @@ void riscv_fill_hwcap(void) elf_hwcap &= this_hwcap; else elf_hwcap = this_hwcap; + + if (riscv_isa) + riscv_isa &= this_isa; + else + riscv_isa = this_isa; } /* We don't support systems with F but without D, so mask those out @@ -64,7 +87,17 @@ void riscv_fill_hwcap(void) elf_hwcap &= ~COMPAT_HWCAP_ISA_F; } - pr_info("elf_hwcap is 0x%lx\n", elf_hwcap); + memset(print_str, 0, sizeof(print_str)); + for (i = 0, j = 0; i < BITS_PER_LONG; i++) + if (riscv_isa & (1UL << i)) + print_str[j++] = (char)('a' + i); + pr_info("riscv: ISA extensions %s\n", print_str); + + memset(print_str, 0, sizeof(print_str)); + for (i = 0, j = 0; i < BITS_PER_LONG; i++) + if (elf_hwcap & (1UL << i)) + print_str[j++] = (char)('a' + i); + pr_info("riscv: ELF capabilities %s\n", print_str); #ifdef CONFIG_FPU if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))