| Message ID | 20190803042723.7163-5-atish.patra@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Miscellaneous fixes | expand |
On Fri, 2 Aug 2019, Atish Patra wrote: > Since the RISC-V specification states that ISA description strings are > case-insensitive, there's no functional difference between mixed-case, > upper-case, and lower-case ISA strings. Thus, to simplify parsing, > specify that the letters present in "riscv,isa" must be all lowercase. > > Suggested-by: Paul Walmsley <paul.walmsley@sifive.com> > Signed-off-by: Atish Patra <atish.patra@wdc.com> Thanks, queued for v5.3-rc4. - Paul
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c899111aa5e3..9d3fe6aada2b 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -50,6 +50,10 @@ properties: User-Level ISA document, available from https://riscv.org/specifications/ + While the isa strings in ISA specification are case + insensitive, letters in the riscv,isa string must be all + lowercase to simplify parsing. + timebase-frequency: type: integer minimum: 1
Since the RISC-V specification states that ISA description strings are case-insensitive, there's no functional difference between mixed-case, upper-case, and lower-case ISA strings. Thus, to simplify parsing, specify that the letters present in "riscv,isa" must be all lowercase. Suggested-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 4 ++++ 1 file changed, 4 insertions(+)