[12/15] riscv: use the correct interrupt levels for M-mode

Message ID	20190813154747.24256-13-hch@lst.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org> From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Subject: [PATCH 12/15] riscv: use the correct interrupt levels for M-mode Date: Tue, 13 Aug 2019 17:47:44 +0200 Message-Id: <20190813154747.24256-13-hch@lst.de> In-Reply-To: <20190813154747.24256-1-hch@lst.de> References: <20190813154747.24256-1-hch@lst.de> MIME-Version: 1.0 Precedence: list Cc: Damien Le Moal <damien.lemoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org
Series	[01/15] irqchip/sifive-plic: set max threshold for ignored handlers \| expand [01/15] irqchip/sifive-plic: set max threshold for ignored handlers [02/15] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm [03/15] riscv: refactor the IPI code [04/15] riscv: abstract out CSR names for supervisor vs machine mode [05/15] riscv: improve the default power off implementation [06/15] riscv: provide a flat entry loader [07/15] riscv: read the hart ID from mhartid on boot [08/15] riscv: provide native clint access for M-mode [09/15] riscv: implement remote sfence.i natively for M-mode [10/15] riscv: poison SBI calls for M-mode [11/15] riscv: don't allow selecting SBI-based drivers for M-mode [12/15] riscv: use the correct interrupt levels for M-mode [13/15] riscv: clear the instruction cache and all registers when booting [14/15] riscv: add nommu support [15/15] riscv: disable the EFI PECOFF header for M-mode

Message ID

20190813154747.24256-13-hch@lst.de (mailing list archive)

State

New, archived

Headers

From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
 Paul Walmsley <paul.walmsley@sifive.com>
Subject: [PATCH 12/15] riscv: use the correct interrupt levels for M-mode
Date: Tue, 13 Aug 2019 17:47:44 +0200
Message-Id: <20190813154747.24256-13-hch@lst.de>
In-Reply-To: <20190813154747.24256-1-hch@lst.de>
References: <20190813154747.24256-1-hch@lst.de>
MIME-Version: 1.0
Precedence: list
Cc: Damien Le Moal <damien.lemoal@wdc.com>, linux-riscv@lists.infradead.org,
 linux-kernel@vger.kernel.org
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 linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org

Series

[01/15] irqchip/sifive-plic: set max threshold for ignored handlers | expand

Commit Message

Christoph Hellwig Aug. 13, 2019, 3:47 p.m. UTC

The numerical levels for External/Timer/Software interrupts differ
between S-mode and M-mode.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/riscv/kernel/irq.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c
index 804ff70bb853..9566aabbe50b 100644
--- a/arch/riscv/kernel/irq.c
+++ b/arch/riscv/kernel/irq.c
@@ -14,9 +14,15 @@ 
 /*
  * Possible interrupt causes:
  */
-#define INTERRUPT_CAUSE_SOFTWARE	IRQ_S_SOFT
-#define INTERRUPT_CAUSE_TIMER		IRQ_S_TIMER
-#define INTERRUPT_CAUSE_EXTERNAL	IRQ_S_EXT
+#ifdef CONFIG_M_MODE
+# define INTERRUPT_CAUSE_SOFTWARE	IRQ_M_SOFT
+# define INTERRUPT_CAUSE_TIMER		IRQ_M_TIMER
+# define INTERRUPT_CAUSE_EXTERNAL	IRQ_M_EXT
+#else
+# define INTERRUPT_CAUSE_SOFTWARE	IRQ_S_SOFT
+# define INTERRUPT_CAUSE_TIMER		IRQ_S_TIMER
+# define INTERRUPT_CAUSE_EXTERNAL	IRQ_S_EXT
+#endif /* CONFIG_M_MODE */
 
 int arch_show_interrupts(struct seq_file *p, int prec)
 {

[12/15] riscv: use the correct interrupt levels for M-mode

Commit Message

Patch