[15/20] riscv: read the hart ID from mhartid on boot

Message ID	20190903093239.21278-16-hch@lst.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=37eK=W6=lists.infradead.org=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9FADD22CF8 From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Subject: [PATCH 15/20] riscv: read the hart ID from mhartid on boot Date: Tue, 3 Sep 2019 11:32:34 +0200 Message-Id: <20190903093239.21278-16-hch@lst.de> In-Reply-To: <20190903093239.21278-1-hch@lst.de> References: <20190903093239.21278-1-hch@lst.de> MIME-Version: 1.0 Precedence: list Cc: Atish Patra <atish.patra@wdc.com>, Damien Le Moal <Damien.LeMoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org
Series	[01/20] irqchip/sifive-plic: set max threshold for ignored handlers \| expand [01/20] irqchip/sifive-plic: set max threshold for ignored handlers [02/20] riscv: refactor the IPI code [03/20] riscv: cleanup send_ipi_mask [04/20] riscv: optimize send_ipi_single [05/20] riscv: cleanup riscv_cpuid_to_hartid_mask [06/20] riscv: don't use the rdtime(h) pseudo-instructions [07/20] riscv: move the TLB flush logic out of line [08/20] riscv: abstract out CSR names for supervisor vs machine mode [09/20] riscv: don't allow selecting SBI based drivers for M-mode [10/20] riscv: poison SBI calls for M-mode [11/20] riscv: cleanup the default power off implementation [12/20] riscv: implement remote sfence.i using IPIs [13/20] riscv: add support for MMIO access to the timer registers [14/20] riscv: provide native clint access for M-mode [15/20] riscv: read the hart ID from mhartid on boot [16/20] riscv: use the correct interrupt levels for M-mode [17/20] riscv: clear the instruction cache and all registers when booting [18/20] riscv: add nommu support [19/20] riscv: provide a flat image loader [20/20] riscv: disable the EFI PECOFF header for M-mode

Message ID

20190903093239.21278-16-hch@lst.de (mailing list archive)

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New, archived

Headers

DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9FADD22CF8
From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
 Paul Walmsley <paul.walmsley@sifive.com>
Subject: [PATCH 15/20] riscv: read the hart ID from mhartid on boot
Date: Tue,  3 Sep 2019 11:32:34 +0200
Message-Id: <20190903093239.21278-16-hch@lst.de>
In-Reply-To: <20190903093239.21278-1-hch@lst.de>
References: <20190903093239.21278-1-hch@lst.de>
MIME-Version: 1.0
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Cc: Atish Patra <atish.patra@wdc.com>, Damien Le Moal <Damien.LeMoal@wdc.com>,
 linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
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Series

[01/20] irqchip/sifive-plic: set max threshold for ignored handlers | expand

Commit Message

Christoph Hellwig Sept. 3, 2019, 9:32 a.m. UTC

From: Damien Le Moal <Damien.LeMoal@wdc.com>

When in M-Mode, we can use the mhartid CSR to get the ID of the running
HART. Doing so, direct M-Mode boot without firmware is possible.

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
---
 arch/riscv/include/asm/csr.h | 1 +
 arch/riscv/kernel/head.S     | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 0dae5c361f29..d0b5113e1a54 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -81,6 +81,7 @@ 
 #define SIE_SEIE		(_AC(0x1, UL) << IRQ_S_EXT)
 
 /* symbolic CSR names: */
+#define CSR_MHARTID		0xf14
 #define CSR_MSTATUS		0x300
 #define CSR_MIE			0x304
 #define CSR_MTVEC		0x305
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index bb96bb7b95d2..e0350499d7a4 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -50,6 +50,14 @@  _start_kernel:
 	csrw CSR_XIE, zero
 	csrw CSR_XIP, zero
 
+#ifdef CONFIG_RISCV_M_MODE
+	/*
+	 * The hartid in a0 is expected later on, and we have no firmware
+	 * to hand it to us.
+	 */
+	csrr a0, CSR_MHARTID
+#endif
+
 	/* Load the global pointer */
 .option push
 .option norelax

[15/20] riscv: read the hart ID from mhartid on boot

Commit Message

Patch