[16/20] riscv: use the correct interrupt levels for M-mode

Message ID	20190903093239.21278-17-hch@lst.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=37eK=W6=lists.infradead.org=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A425722D6D From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Subject: [PATCH 16/20] riscv: use the correct interrupt levels for M-mode Date: Tue, 3 Sep 2019 11:32:35 +0200 Message-Id: <20190903093239.21278-17-hch@lst.de> In-Reply-To: <20190903093239.21278-1-hch@lst.de> References: <20190903093239.21278-1-hch@lst.de> MIME-Version: 1.0 Precedence: list Cc: Damien Le Moal <damien.lemoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org
Series	[01/20] irqchip/sifive-plic: set max threshold for ignored handlers \| expand [01/20] irqchip/sifive-plic: set max threshold for ignored handlers [02/20] riscv: refactor the IPI code [03/20] riscv: cleanup send_ipi_mask [04/20] riscv: optimize send_ipi_single [05/20] riscv: cleanup riscv_cpuid_to_hartid_mask [06/20] riscv: don't use the rdtime(h) pseudo-instructions [07/20] riscv: move the TLB flush logic out of line [08/20] riscv: abstract out CSR names for supervisor vs machine mode [09/20] riscv: don't allow selecting SBI based drivers for M-mode [10/20] riscv: poison SBI calls for M-mode [11/20] riscv: cleanup the default power off implementation [12/20] riscv: implement remote sfence.i using IPIs [13/20] riscv: add support for MMIO access to the timer registers [14/20] riscv: provide native clint access for M-mode [15/20] riscv: read the hart ID from mhartid on boot [16/20] riscv: use the correct interrupt levels for M-mode [17/20] riscv: clear the instruction cache and all registers when booting [18/20] riscv: add nommu support [19/20] riscv: provide a flat image loader [20/20] riscv: disable the EFI PECOFF header for M-mode

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20190903093239.21278-17-hch@lst.de (mailing list archive)

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New, archived

Headers

DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A425722D6D
From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
 Paul Walmsley <paul.walmsley@sifive.com>
Subject: [PATCH 16/20] riscv: use the correct interrupt levels for M-mode
Date: Tue,  3 Sep 2019 11:32:35 +0200
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Series

[01/20] irqchip/sifive-plic: set max threshold for ignored handlers | expand

Commit Message

Christoph Hellwig Sept. 3, 2019, 9:32 a.m. UTC

The numerical levels for External/Timer/Software interrupts differ
between S-mode and M-mode.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/riscv/kernel/irq.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c
index 804ff70bb853..dbd1fd7c22e4 100644
--- a/arch/riscv/kernel/irq.c
+++ b/arch/riscv/kernel/irq.c
@@ -14,9 +14,15 @@ 
 /*
  * Possible interrupt causes:
  */
-#define INTERRUPT_CAUSE_SOFTWARE	IRQ_S_SOFT
-#define INTERRUPT_CAUSE_TIMER		IRQ_S_TIMER
-#define INTERRUPT_CAUSE_EXTERNAL	IRQ_S_EXT
+#ifdef CONFIG_RISCV_M_MODE
+# define INTERRUPT_CAUSE_SOFTWARE	IRQ_M_SOFT
+# define INTERRUPT_CAUSE_TIMER		IRQ_M_TIMER
+# define INTERRUPT_CAUSE_EXTERNAL	IRQ_M_EXT
+#else
+# define INTERRUPT_CAUSE_SOFTWARE	IRQ_S_SOFT
+# define INTERRUPT_CAUSE_TIMER		IRQ_S_TIMER
+# define INTERRUPT_CAUSE_EXTERNAL	IRQ_S_EXT
+#endif /* CONFIG_RISCV_M_MODE */
 
 int arch_show_interrupts(struct seq_file *p, int prec)
 {

[16/20] riscv: use the correct interrupt levels for M-mode

Commit Message

Patch