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[4/4] Documentation: riscv: boot: Don't mention big-endian

Message ID 20190913192433.4316-5-palmer@sifive.com (mailing list archive)
State New, archived
Headers show
Series Documentation: riscv: Image cleanups | expand

Commit Message

Palmer Dabbelt Sept. 13, 2019, 7:24 p.m. UTC
The documentation defines a flag to indicate big endian systems, but
doesn't define what that flag actually means -- for example:

* Are the other fields BE or LE?
* Does the BE format assume the bootloader enters BE mode, is there a
  kernel stub that does so, or are we adding extra BE instructions?

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 Documentation/riscv/boot-image-header.txt | 3 ---
 1 file changed, 3 deletions(-)
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Patch

diff --git a/Documentation/riscv/boot-image-header.txt b/Documentation/riscv/boot-image-header.txt
index e325d1c9ad4c..d3efaf374b27 100644
--- a/Documentation/riscv/boot-image-header.txt
+++ b/Documentation/riscv/boot-image-header.txt
@@ -42,8 +42,5 @@  Notes:
   header extendible in future. One example would be to accommodate ISA
   extension for RISC-V in future. For current version, it is set to be zero.
 
-- In current header, the flag field has only one field.
-	Bit 0: Kernel endianness. 1 if BE, 0 if LE.
-
 - Image size is mandatory for boot loader to load kernel image. Booting will
   fail otherwise.