diff mbox series

[v2,6/9] riscv: Add Kendryte K210 device tree

Message ID 20200312051107.1454880-7-damien.lemoal@wdc.com (mailing list archive)
State New, archived
Headers show
Series Kendryte k210 SoC boards support | expand

Commit Message

Damien Le Moal March 12, 2020, 5:11 a.m. UTC 
Add a generic device tree for Kendryte K210 SoC based boards. This (for
now) very simple device tree works for the Kendryte KD233 development
board, the Sipeed MAIX M1 Dan Dock board and the Sipeed MAIXDUINO board.

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
---
 arch/riscv/boot/dts/Makefile           |   1 +
 arch/riscv/boot/dts/kendryte/Makefile  |   2 +
 arch/riscv/boot/dts/kendryte/k210.dts  |  23 +++++
 arch/riscv/boot/dts/kendryte/k210.dtsi | 117 +++++++++++++++++++++++++
 include/dt-bindings/clock/k210-clk.h   |  20 +++++
 5 files changed, 163 insertions(+)
 create mode 100644 arch/riscv/boot/dts/kendryte/Makefile
 create mode 100644 arch/riscv/boot/dts/kendryte/k210.dts
 create mode 100644 arch/riscv/boot/dts/kendryte/k210.dtsi
 create mode 100644 include/dt-bindings/clock/k210-clk.h

Comments

Sean Anderson March 12, 2020, 6:16 p.m. UTC | #1 
On 3/12/20 1:11 AM, Damien Le Moal wrote:
> Add a generic device tree for Kendryte K210 SoC based boards. This (for
> now) very simple device tree works for the Kendryte KD233 development
> board, the Sipeed MAIX M1 Dan Dock board and the Sipeed MAIXDUINO board.
> 
> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
> ---
>  arch/riscv/boot/dts/Makefile           |   1 +
>  arch/riscv/boot/dts/kendryte/Makefile  |   2 +
>  arch/riscv/boot/dts/kendryte/k210.dts  |  23 +++++
>  arch/riscv/boot/dts/kendryte/k210.dtsi | 117 +++++++++++++++++++++++++
>  include/dt-bindings/clock/k210-clk.h   |  20 +++++
>  5 files changed, 163 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/kendryte/Makefile
>  create mode 100644 arch/riscv/boot/dts/kendryte/k210.dts
>  create mode 100644 arch/riscv/boot/dts/kendryte/k210.dtsi
>  create mode 100644 include/dt-bindings/clock/k210-clk.h
> 
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index 0bf2669aa12d..87815557f2db 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -3,4 +3,5 @@ ifneq ($(CONFIG_BUILTIN_DTB_SOURCE),"")
>  obj-$(CONFIG_USE_BUILTIN_DTB) += $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_SOURCE)).dtb.o
>  else
>  subdir-y += sifive
> +subdir-y += kendryte
>  endif
> diff --git a/arch/riscv/boot/dts/kendryte/Makefile b/arch/riscv/boot/dts/kendryte/Makefile
> new file mode 100644
> index 000000000000..815444e69e89
> --- /dev/null
> +++ b/arch/riscv/boot/dts/kendryte/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_SOC_KENDRYTE) += k210.dtb
> diff --git a/arch/riscv/boot/dts/kendryte/k210.dts b/arch/riscv/boot/dts/kendryte/k210.dts
> new file mode 100644
> index 000000000000..0d1f28fce6b2
> --- /dev/null
> +++ b/arch/riscv/boot/dts/kendryte/k210.dts
> @@ -0,0 +1,23 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020 Western Digital Corporation or its affiliates.
> + */
> +
> +/dts-v1/;
> +
> +#include "k210.dtsi"
> +
> +/ {
> +	model = "Kendryte K210 generic";
> +	compatible = "kendryte,k210";
> +
> +	chosen {
> +		bootargs = "earlycon console=ttySIF0";
> +		stdout-path = "serial0";
> +	};
> +};
> +
> +&uarths0 {
> +	status = "okay";
> +};
> +
> diff --git a/arch/riscv/boot/dts/kendryte/k210.dtsi b/arch/riscv/boot/dts/kendryte/k210.dtsi
> new file mode 100644
> index 000000000000..88f28a3fd337
> --- /dev/null
> +++ b/arch/riscv/boot/dts/kendryte/k210.dtsi
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
> + * Copyright (C) 2020 Western Digital Corporation or its affiliates.
> + */
> +#include <dt-bindings/clock/k210-clk.h>
> +
> +/ {
> +	/*
> +	 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
> +	 * wide, and the upper half of all addresses is ignored.
> +	 */
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	compatible = "kendryte,k210";
> +
> +	aliases {
> +		serial0 = &uarths0;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		timebase-frequency = <7800000>;
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			reg = <0>;
> +			compatible = "kendryte,k210", "sifive,rocket0", "riscv";
> +			riscv,isa = "rv64imafdc";
> +			mmu-type = "none";
> +			i-cache-size = <0x8000>;
> +			i-cache-block-size = <64>;
> +			d-cache-size = <0x8000>;
> +			d-cache-block-size = <64>;
> +			clocks = <&sysctl K210_CLK_CPU>;
> +			clock-frequency = <390000000>;
> +			cpu0_intc: interrupt-controller {
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +				compatible = "riscv,cpu-intc";
> +			};
> +		};
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			reg = <1>;
> +			compatible = "kendryte,k210", "sifive,rocket0", "riscv";
> +			riscv,isa = "rv64imafdc";
> +			mmu-type = "none";

Perhaps add a comment? The mmu is still sv39, even if the kernel is NOMMU.

> +			i-cache-size = <0x8000>;
> +			i-cache-block-size = <64>; /* bogus */

These comments should be removed to match the bindings above.

> +			d-cache-size = <0x8000>;
> +			d-cache-block-size = <64>; /* bogus */
> +			clocks = <&sysctl K210_CLK_CPU>;
> +			clock-frequency = <390000000>;
> +			cpu1_intc: interrupt-controller {
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +				compatible = "riscv,cpu-intc";
> +			};
> +		};
> +	};
> +
> +	sram: memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x80000000 0x400000>,
> +		      <0x80400000 0x200000>,
> +		      <0x80600000 0x200000>;
> +		reg-names = "sram0", "sram1", "aisram";
> +	};
> +
> +	clocks {
> +		in0: oscillator {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <26000000>;
> +		};
> +	};
> +
> +	soc {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "kendryte,k210-soc", "simple-bus";
> +		ranges;
> +		interrupt-parent = <&plic0>;
> +
> +		sysctl: sysctl@50440000 {
> +			compatible = "kendryte,k210-sysctl", "syscon";
> +			reg = <0x50440000 0x1000>;
> +			#clock-cells = <1>;
> +		};

Still think this should be modeled as an mfd.

> +
> +		clint0: interrupt-controller@2000000 {
> +			compatible = "riscv,clint0";
> +			reg = <0x2000000 0xC000>;
> +			interrupts-extended = <&cpu0_intc 3>,  <&cpu1_intc 3>;
> +			clocks = <&sysctl K210_CLK_ACLK>;
> +		};
> +
> +		plic0: interrupt-controller@c000000 {
> +			#interrupt-cells = <1>;
> +			interrupt-controller;
> +			compatible = "kendryte,k210-plic0", "riscv,plic0";
> +			reg = <0xC000000 0x4000000>;
> +			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 0xffffffff>,
> +					      <&cpu1_intc 11>, <&cpu1_intc 0xffffffff>;
> +			riscv,ndev = <65>;
> +			riscv,max-priority = <7>;
> +		};
> +
> +		uarths0: serial@38000000 {
> +			compatible = "kendryte,k210-uarths", "sifive,uart0";
> +			reg = <0x38000000 0x1000>;
> +			interrupts = <33>;
> +			clocks = <&sysctl K210_CLK_CPU>;
> +		};
> +	};
> +};
> diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h
> new file mode 100644
> index 000000000000..5a2fd64d1a49
> --- /dev/null
> +++ b/include/dt-bindings/clock/k210-clk.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
> + * Copyright (c) 2020 Western Digital Corporation or its affiliates.
> + */
> +#ifndef K210_CLK_H
> +#define K210_CLK_H
> +
> +/*
> + * Arbitrary identifiers for clocks.
> + * The structure is: in0 -> pll0 -> aclk -> cpu
> + *
> + * Since we use the hardware defaults for now, set all these to the same clock.
> + */
> +#define K210_CLK_PLL0   0
> +#define K210_CLK_PLL1   0
> +#define K210_CLK_ACLK   0
> +#define K210_CLK_CPU    0
> +
> +#endif /* K210_CLK_H */
> 

--Sean
Damien Le Moal March 13, 2020, 5:29 a.m. UTC | #2 
On Thu, 2020-03-12 at 14:16 -0400, Sean Anderson wrote:
> On 3/12/20 1:11 AM, Damien Le Moal wrote:
> > Add a generic device tree for Kendryte K210 SoC based boards. This (for
> > now) very simple device tree works for the Kendryte KD233 development
> > board, the Sipeed MAIX M1 Dan Dock board and the Sipeed MAIXDUINO board.
> > 
> > Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
> > ---
> >  arch/riscv/boot/dts/Makefile           |   1 +
> >  arch/riscv/boot/dts/kendryte/Makefile  |   2 +
> >  arch/riscv/boot/dts/kendryte/k210.dts  |  23 +++++
> >  arch/riscv/boot/dts/kendryte/k210.dtsi | 117 +++++++++++++++++++++++++
> >  include/dt-bindings/clock/k210-clk.h   |  20 +++++
> >  5 files changed, 163 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/kendryte/Makefile
> >  create mode 100644 arch/riscv/boot/dts/kendryte/k210.dts
> >  create mode 100644 arch/riscv/boot/dts/kendryte/k210.dtsi
> >  create mode 100644 include/dt-bindings/clock/k210-clk.h
> > 
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index 0bf2669aa12d..87815557f2db 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -3,4 +3,5 @@ ifneq ($(CONFIG_BUILTIN_DTB_SOURCE),"")
> >  obj-$(CONFIG_USE_BUILTIN_DTB) += $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_SOURCE)).dtb.o
> >  else
> >  subdir-y += sifive
> > +subdir-y += kendryte
> >  endif
> > diff --git a/arch/riscv/boot/dts/kendryte/Makefile b/arch/riscv/boot/dts/kendryte/Makefile
> > new file mode 100644
> > index 000000000000..815444e69e89
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/kendryte/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_SOC_KENDRYTE) += k210.dtb
> > diff --git a/arch/riscv/boot/dts/kendryte/k210.dts b/arch/riscv/boot/dts/kendryte/k210.dts
> > new file mode 100644
> > index 000000000000..0d1f28fce6b2
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/kendryte/k210.dts
> > @@ -0,0 +1,23 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2020 Western Digital Corporation or its affiliates.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "k210.dtsi"
> > +
> > +/ {
> > +	model = "Kendryte K210 generic";
> > +	compatible = "kendryte,k210";
> > +
> > +	chosen {
> > +		bootargs = "earlycon console=ttySIF0";
> > +		stdout-path = "serial0";
> > +	};
> > +};
> > +
> > +&uarths0 {
> > +	status = "okay";
> > +};
> > +
> > diff --git a/arch/riscv/boot/dts/kendryte/k210.dtsi b/arch/riscv/boot/dts/kendryte/k210.dtsi
> > new file mode 100644
> > index 000000000000..88f28a3fd337
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/kendryte/k210.dtsi
> > @@ -0,0 +1,117 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
> > + * Copyright (C) 2020 Western Digital Corporation or its affiliates.
> > + */
> > +#include <dt-bindings/clock/k210-clk.h>
> > +
> > +/ {
> > +	/*
> > +	 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
> > +	 * wide, and the upper half of all addresses is ignored.
> > +	 */
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +	compatible = "kendryte,k210";
> > +
> > +	aliases {
> > +		serial0 = &uarths0;
> > +	};
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		timebase-frequency = <7800000>;
> > +		cpu0: cpu@0 {
> > +			device_type = "cpu";
> > +			reg = <0>;
> > +			compatible = "kendryte,k210", "sifive,rocket0", "riscv";
> > +			riscv,isa = "rv64imafdc";
> > +			mmu-type = "none";
> > +			i-cache-size = <0x8000>;
> > +			i-cache-block-size = <64>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-block-size = <64>;
> > +			clocks = <&sysctl K210_CLK_CPU>;
> > +			clock-frequency = <390000000>;
> > +			cpu0_intc: interrupt-controller {
> > +				#interrupt-cells = <1>;
> > +				interrupt-controller;
> > +				compatible = "riscv,cpu-intc";
> > +			};
> > +		};
> > +		cpu1: cpu@1 {
> > +			device_type = "cpu";
> > +			reg = <1>;
> > +			compatible = "kendryte,k210", "sifive,rocket0", "riscv";
> > +			riscv,isa = "rv64imafdc";
> > +			mmu-type = "none";
> 
> Perhaps add a comment? The mmu is still sv39, even if the kernel is NOMMU.

Yes, will do. I want to keep this entry as "none" because we cannot
support the 1.9 spec MMU. So yes, clarifying this point will be good.

> 
> > +			i-cache-size = <0x8000>;
> > +			i-cache-block-size = <64>; /* bogus */
> 
> These comments should be removed to match the bindings above.

Oops. Yes. Missed that one :)

> 
> > +			d-cache-size = <0x8000>;
> > +			d-cache-block-size = <64>; /* bogus */
> > +			clocks = <&sysctl K210_CLK_CPU>;
> > +			clock-frequency = <390000000>;
> > +			cpu1_intc: interrupt-controller {
> > +				#interrupt-cells = <1>;
> > +				interrupt-controller;
> > +				compatible = "riscv,cpu-intc";
> > +			};
> > +		};
> > +	};
> > +
> > +	sram: memory@80000000 {
> > +		device_type = "memory";
> > +		reg = <0x80000000 0x400000>,
> > +		      <0x80400000 0x200000>,
> > +		      <0x80600000 0x200000>;
> > +		reg-names = "sram0", "sram1", "aisram";
> > +	};
> > +
> > +	clocks {
> > +		in0: oscillator {
> > +			compatible = "fixed-clock";
> > +			#clock-cells = <0>;
> > +			clock-frequency = <26000000>;
> > +		};
> > +	};
> > +
> > +	soc {
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		compatible = "kendryte,k210-soc", "simple-bus";
> > +		ranges;
> > +		interrupt-parent = <&plic0>;
> > +
> > +		sysctl: sysctl@50440000 {
> > +			compatible = "kendryte,k210-sysctl", "syscon";
> > +			reg = <0x50440000 0x1000>;
> > +			#clock-cells = <1>;
> > +		};
> 
> Still think this should be modeled as an mfd.

Yes. Absolutely. That will be needed for adding support for GPIO, SD
card etc. However, I do not want to do this now and leave this work for
another series on top of this one. Would you agree with this approach ?

> 
> > +
> > +		clint0: interrupt-controller@2000000 {
> > +			compatible = "riscv,clint0";
> > +			reg = <0x2000000 0xC000>;
> > +			interrupts-extended = <&cpu0_intc 3>,  <&cpu1_intc 3>;
> > +			clocks = <&sysctl K210_CLK_ACLK>;
> > +		};
> > +
> > +		plic0: interrupt-controller@c000000 {
> > +			#interrupt-cells = <1>;
> > +			interrupt-controller;
> > +			compatible = "kendryte,k210-plic0", "riscv,plic0";
> > +			reg = <0xC000000 0x4000000>;
> > +			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 0xffffffff>,
> > +					      <&cpu1_intc 11>, <&cpu1_intc 0xffffffff>;
> > +			riscv,ndev = <65>;
> > +			riscv,max-priority = <7>;
> > +		};
> > +
> > +		uarths0: serial@38000000 {
> > +			compatible = "kendryte,k210-uarths", "sifive,uart0";
> > +			reg = <0x38000000 0x1000>;
> > +			interrupts = <33>;
> > +			clocks = <&sysctl K210_CLK_CPU>;
> > +		};
> > +	};
> > +};
> > diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h
> > new file mode 100644
> > index 000000000000..5a2fd64d1a49
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/k210-clk.h
> > @@ -0,0 +1,20 @@
> > +/* SPDX-License-Identifier: GPL-2.0-or-later */
> > +/*
> > + * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
> > + * Copyright (c) 2020 Western Digital Corporation or its affiliates.
> > + */
> > +#ifndef K210_CLK_H
> > +#define K210_CLK_H
> > +
> > +/*
> > + * Arbitrary identifiers for clocks.
> > + * The structure is: in0 -> pll0 -> aclk -> cpu
> > + *
> > + * Since we use the hardware defaults for now, set all these to the same clock.
> > + */
> > +#define K210_CLK_PLL0   0
> > +#define K210_CLK_PLL1   0
> > +#define K210_CLK_ACLK   0
> > +#define K210_CLK_CPU    0
> > +
> > +#endif /* K210_CLK_H */
> > 
> 
> --Sean
> 
>
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 0bf2669aa12d..87815557f2db 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -3,4 +3,5 @@  ifneq ($(CONFIG_BUILTIN_DTB_SOURCE),"")
 obj-$(CONFIG_USE_BUILTIN_DTB) += $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_SOURCE)).dtb.o
 else
 subdir-y += sifive
+subdir-y += kendryte
 endif
diff --git a/arch/riscv/boot/dts/kendryte/Makefile b/arch/riscv/boot/dts/kendryte/Makefile
new file mode 100644
index 000000000000..815444e69e89
--- /dev/null
+++ b/arch/riscv/boot/dts/kendryte/Makefile
@@ -0,0 +1,2 @@ 
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_KENDRYTE) += k210.dtb
diff --git a/arch/riscv/boot/dts/kendryte/k210.dts b/arch/riscv/boot/dts/kendryte/k210.dts
new file mode 100644
index 000000000000..0d1f28fce6b2
--- /dev/null
+++ b/arch/riscv/boot/dts/kendryte/k210.dts
@@ -0,0 +1,23 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Western Digital Corporation or its affiliates.
+ */
+
+/dts-v1/;
+
+#include "k210.dtsi"
+
+/ {
+	model = "Kendryte K210 generic";
+	compatible = "kendryte,k210";
+
+	chosen {
+		bootargs = "earlycon console=ttySIF0";
+		stdout-path = "serial0";
+	};
+};
+
+&uarths0 {
+	status = "okay";
+};
+
diff --git a/arch/riscv/boot/dts/kendryte/k210.dtsi b/arch/riscv/boot/dts/kendryte/k210.dtsi
new file mode 100644
index 000000000000..88f28a3fd337
--- /dev/null
+++ b/arch/riscv/boot/dts/kendryte/k210.dtsi
@@ -0,0 +1,117 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
+ * Copyright (C) 2020 Western Digital Corporation or its affiliates.
+ */
+#include <dt-bindings/clock/k210-clk.h>
+
+/ {
+	/*
+	 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
+	 * wide, and the upper half of all addresses is ignored.
+	 */
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "kendryte,k210";
+
+	aliases {
+		serial0 = &uarths0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <7800000>;
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			compatible = "kendryte,k210", "sifive,rocket0", "riscv";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "none";
+			i-cache-size = <0x8000>;
+			i-cache-block-size = <64>;
+			d-cache-size = <0x8000>;
+			d-cache-block-size = <64>;
+			clocks = <&sysctl K210_CLK_CPU>;
+			clock-frequency = <390000000>;
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			reg = <1>;
+			compatible = "kendryte,k210", "sifive,rocket0", "riscv";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "none";
+			i-cache-size = <0x8000>;
+			i-cache-block-size = <64>; /* bogus */
+			d-cache-size = <0x8000>;
+			d-cache-block-size = <64>; /* bogus */
+			clocks = <&sysctl K210_CLK_CPU>;
+			clock-frequency = <390000000>;
+			cpu1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+	};
+
+	sram: memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x400000>,
+		      <0x80400000 0x200000>,
+		      <0x80600000 0x200000>;
+		reg-names = "sram0", "sram1", "aisram";
+	};
+
+	clocks {
+		in0: oscillator {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <26000000>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "kendryte,k210-soc", "simple-bus";
+		ranges;
+		interrupt-parent = <&plic0>;
+
+		sysctl: sysctl@50440000 {
+			compatible = "kendryte,k210-sysctl", "syscon";
+			reg = <0x50440000 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		clint0: interrupt-controller@2000000 {
+			compatible = "riscv,clint0";
+			reg = <0x2000000 0xC000>;
+			interrupts-extended = <&cpu0_intc 3>,  <&cpu1_intc 3>;
+			clocks = <&sysctl K210_CLK_ACLK>;
+		};
+
+		plic0: interrupt-controller@c000000 {
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			compatible = "kendryte,k210-plic0", "riscv,plic0";
+			reg = <0xC000000 0x4000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 0xffffffff>,
+					      <&cpu1_intc 11>, <&cpu1_intc 0xffffffff>;
+			riscv,ndev = <65>;
+			riscv,max-priority = <7>;
+		};
+
+		uarths0: serial@38000000 {
+			compatible = "kendryte,k210-uarths", "sifive,uart0";
+			reg = <0x38000000 0x1000>;
+			interrupts = <33>;
+			clocks = <&sysctl K210_CLK_CPU>;
+		};
+	};
+};
diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h
new file mode 100644
index 000000000000..5a2fd64d1a49
--- /dev/null
+++ b/include/dt-bindings/clock/k210-clk.h
@@ -0,0 +1,20 @@ 
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ */
+#ifndef K210_CLK_H
+#define K210_CLK_H
+
+/*
+ * Arbitrary identifiers for clocks.
+ * The structure is: in0 -> pll0 -> aclk -> cpu
+ *
+ * Since we use the hardware defaults for now, set all these to the same clock.
+ */
+#define K210_CLK_PLL0   0
+#define K210_CLK_PLL1   0
+#define K210_CLK_ACLK   0
+#define K210_CLK_CPU    0
+
+#endif /* K210_CLK_H */