| Message ID | 20200408165802.167546-4-palmer@dabbelt.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/3] RISC-V: Allow device trees to be built into the kernel | expand |
On 2020/04/09 1:58, Palmer Dabbelt wrote: > From: Palmer Dabbelt <palmerdabbelt@google.com> > > The RISC-V ISA manual says that PMPs are WARL, but it appears the K210 > doesn't implement them and instead traps on the unsupported accesses. > This patch handles those traps by just skipping the PMP > initialization entirely, under the theory that machines that trap on PMP > accesses must allow memory accesses as otherwise they're pretty useless. > > Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> This one works: Tested-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Damien Le Moal <damien.lemoal@wdc.com> Testing/hacking the other 2 patches of the series now. > --- > arch/riscv/kernel/head.S | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S > index 98a406474e7d..7ed1b22950fd 100644 > --- a/arch/riscv/kernel/head.S > +++ b/arch/riscv/kernel/head.S > @@ -161,11 +161,20 @@ ENTRY(_start_kernel) > /* Reset all registers except ra, a0, a1 */ > call reset_regs > > - /* Setup a PMP to permit access to all of memory. */ > + /* > + * Setup a PMP to permit access to all of memory. Some machines may > + * not implement PMPs, so we set up a quick trap handler to just skip > + * touching the PMPs on any trap. > + */ > + la a0, pmp_done > + csrw CSR_TVEC, a0 > + > li a0, -1 > csrw CSR_PMPADDR0, a0 > li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X) > csrw CSR_PMPCFG0, a0 > +.align 2 > +pmp_done: > > /* > * The hartid in a0 is expected later on, and we have no firmware >
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 98a406474e7d..7ed1b22950fd 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -161,11 +161,20 @@ ENTRY(_start_kernel) /* Reset all registers except ra, a0, a1 */ call reset_regs - /* Setup a PMP to permit access to all of memory. */ + /* + * Setup a PMP to permit access to all of memory. Some machines may + * not implement PMPs, so we set up a quick trap handler to just skip + * touching the PMPs on any trap. + */ + la a0, pmp_done + csrw CSR_TVEC, a0 + li a0, -1 csrw CSR_PMPADDR0, a0 li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X) csrw CSR_PMPCFG0, a0 +.align 2 +pmp_done: /* * The hartid in a0 is expected later on, and we have no firmware