| Message ID | 20200507150445.174390-2-wangkefeng.wang@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [-next] riscv: perf: RISCV_BASE_PMU should be closeable | expand |
On Thu, 07 May 2020 08:04:45 PDT (-0700), wangkefeng.wang@huawei.com wrote: > As 178e9fc47aae("perf: riscv: preliminary RISC-V support") said, > For RISCV_BASE_PMU, 'this option can also be disable to reduce kernel size', > but it could not work well, we need diable both RISCV_BASE_PMU and > PERF_EVENTS manually, or build error will occur when only disable > RISCV_BASE_PMU. I'm worried this belies a larger issue related to how this PMU stuff works, but we have only one PMU right now so it's not a pressing issue. I've taken this onto fixes. Thanks! > > Cc: Alan Kao <alankao@andestech.com> > Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> > --- > arch/riscv/include/asm/perf_event.h | 8 ++------ > arch/riscv/kernel/Makefile | 2 +- > 2 files changed, 3 insertions(+), 7 deletions(-) > > diff --git a/arch/riscv/include/asm/perf_event.h b/arch/riscv/include/asm/perf_event.h > index 0234048b12bc..062efd3a1d5d 100644 > --- a/arch/riscv/include/asm/perf_event.h > +++ b/arch/riscv/include/asm/perf_event.h > @@ -12,19 +12,14 @@ > #include <linux/ptrace.h> > #include <linux/interrupt.h> > > +#ifdef CONFIG_RISCV_BASE_PMU > #define RISCV_BASE_COUNTERS 2 > > /* > * The RISCV_MAX_COUNTERS parameter should be specified. > */ > > -#ifdef CONFIG_RISCV_BASE_PMU > #define RISCV_MAX_COUNTERS 2 > -#endif > - > -#ifndef RISCV_MAX_COUNTERS > -#error "Please provide a valid RISCV_MAX_COUNTERS for the PMU." > -#endif > > /* > * These are the indexes of bits in counteren register *minus* 1, > @@ -82,6 +77,7 @@ struct riscv_pmu { > int irq; > }; > > +#endif > #ifdef CONFIG_PERF_EVENTS > #define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs > #endif > diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile > index 1f5736e996fd..b355cf485671 100644 > --- a/arch/riscv/kernel/Makefile > +++ b/arch/riscv/kernel/Makefile > @@ -43,7 +43,7 @@ obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o > obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o > obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o > > -obj-$(CONFIG_PERF_EVENTS) += perf_event.o > +obj-$(CONFIG_RISCV_BASE_PMU) += perf_event.o > obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o > obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o > obj-$(CONFIG_RISCV_SBI) += sbi.o
diff --git a/arch/riscv/include/asm/perf_event.h b/arch/riscv/include/asm/perf_event.h index 0234048b12bc..062efd3a1d5d 100644 --- a/arch/riscv/include/asm/perf_event.h +++ b/arch/riscv/include/asm/perf_event.h @@ -12,19 +12,14 @@ #include <linux/ptrace.h> #include <linux/interrupt.h> +#ifdef CONFIG_RISCV_BASE_PMU #define RISCV_BASE_COUNTERS 2 /* * The RISCV_MAX_COUNTERS parameter should be specified. */ -#ifdef CONFIG_RISCV_BASE_PMU #define RISCV_MAX_COUNTERS 2 -#endif - -#ifndef RISCV_MAX_COUNTERS -#error "Please provide a valid RISCV_MAX_COUNTERS for the PMU." -#endif /* * These are the indexes of bits in counteren register *minus* 1, @@ -82,6 +77,7 @@ struct riscv_pmu { int irq; }; +#endif #ifdef CONFIG_PERF_EVENTS #define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs #endif diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 1f5736e996fd..b355cf485671 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -43,7 +43,7 @@ obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o -obj-$(CONFIG_PERF_EVENTS) += perf_event.o +obj-$(CONFIG_RISCV_BASE_PMU) += perf_event.o obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o obj-$(CONFIG_RISCV_SBI) += sbi.o
As 178e9fc47aae("perf: riscv: preliminary RISC-V support") said, For RISCV_BASE_PMU, 'this option can also be disable to reduce kernel size', but it could not work well, we need diable both RISCV_BASE_PMU and PERF_EVENTS manually, or build error will occur when only disable RISCV_BASE_PMU. Cc: Alan Kao <alankao@andestech.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> --- arch/riscv/include/asm/perf_event.h | 8 ++------ arch/riscv/kernel/Makefile | 2 +- 2 files changed, 3 insertions(+), 7 deletions(-)