Message ID | 20201113202550.3693323-2-atish.patra@wdc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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13 Nov 2020 12:12:09 -0800 IronPort-SDR: GudsojcbCJuJ151ef4pw2kB59L4vcuQhce5JpZv1kOCLeSlZOY3DxuQWl8sRQSNPEaiP4Y58V9 ctH2csmrRUyzpU9vVIEmxl5jWe2cWVSzwMRr/OwmrSXGj2vofyzy6bpP6ZKU5/lkXkagF+2YFj pqQVV3+lXQjixM/jYZ7gfbiNN5q2GcqBoAwA+bEMOgOYI7gq1I7SpXX5y5WNy10K3B19Bh2AL4 phSt7zYMHfqjeki68OTkkS34HdI1XX+L4lubt1W88yRRncydlw+azuCOF0smVTvmKs9Wz0SzDb Dbw= WDCIronportException: Internal Received: from usa003372.ad.shared (HELO jedi-01.hgst.com) ([10.86.61.22]) by uls-op-cesaip01.wdc.com with ESMTP; 13 Nov 2020 12:26:12 -0800 From: Atish Patra <atish.patra@wdc.com> To: linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 1/4] RISC-V: Add Microchip PolarFire SoC kconfig option Date: Fri, 13 Nov 2020 12:25:47 -0800 Message-Id: <20201113202550.3693323-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201113202550.3693323-1-atish.patra@wdc.com> References: <20201113202550.3693323-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201113_152616_784118_87A563FC X-CRM114-Status: UNSURE ( 9.29 ) X-CRM114-Notice: Please train this message. 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Add Microchip PolarFire Soc Support
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expand
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diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 8a55f6156661..148ab095966b 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,12 @@ menu "SoC selection" +config SOC_MICROCHIP_POLARFIRE + bool "Microchip PolarFire SoCs" + select MCHP_CLK_PFSOC + select SIFIVE_PLIC + help + This enables support for Microchip PolarFire SoC platforms. + config SOC_SIFIVE bool "SiFive SoCs" select SERIAL_SIFIVE if TTY