| Message ID | 20210203125913.390949-5-damien.lemoal@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V Kendryte K210 support improvements | expand |
On Wed, Feb 03, 2021 at 09:59:01PM +0900, Damien Le Moal wrote: > Add the compatible string "canaan,k210-plic" to the Sifive plic bindings > to indicate the use of the "sifive,plic-1.0.0" IP block in the Canaan > Kendryte K210 SoC. The description is also updated to reflect this > change, that is, that SoCs from other vendors may also use this plic > implementation. > > Cc: Paul Walmsley <paul.walmsley@sifive.com> > Cc: Rob Herring <robh@kernel.org> > Cc: devicetree@vger.kernel.org > Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> > Reviewed-by: Atish Patra <atish.patra@wdc.com> > --- > .../sifive,plic-1.0.0.yaml | 20 ++++++++++++------- > 1 file changed, 13 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > index b9a61c9f7530..04ed7a03c97e 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > @@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: SiFive Platform-Level Interrupt Controller (PLIC) > > description: > - SiFive SOCs include an implementation of the Platform-Level Interrupt Controller > - (PLIC) high-level specification in the RISC-V Privileged Architecture > - specification. The PLIC connects all external interrupts in the system to all > - hart contexts in the system, via the external interrupt source in each hart. > + SiFive SoCs and other RISC-V SoCs include an implementation of the > + Platform-Level Interrupt Controller (PLIC) high-level specification in > + the RISC-V Privileged Architecture specification. The PLIC connects all > + external interrupts in the system to all hart contexts in the system, via > + the external interrupt source in each hart. > > A hart context is a privilege mode in a hardware execution thread. For example, > in an 4 core system with 2-way SMT, you have 8 harts and probably at least two > @@ -41,9 +42,14 @@ maintainers: > > properties: > compatible: > - items: > - - const: sifive,fu540-c000-plic Change this to an 'enum' and add 'canaan,k210-plic'. > - - const: sifive,plic-1.0.0 > + oneOf: > + - items: > + - const: sifive,fu540-c000-plic > + - const: sifive,plic-1.0.0 > + > + - items: > + - const: canaan,k210-plic > + - const: sifive,plic-1.0.0 > > reg: > maxItems: 1 > -- > 2.29.2 >
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index b9a61c9f7530..04ed7a03c97e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SiFive Platform-Level Interrupt Controller (PLIC) description: - SiFive SOCs include an implementation of the Platform-Level Interrupt Controller - (PLIC) high-level specification in the RISC-V Privileged Architecture - specification. The PLIC connects all external interrupts in the system to all - hart contexts in the system, via the external interrupt source in each hart. + SiFive SoCs and other RISC-V SoCs include an implementation of the + Platform-Level Interrupt Controller (PLIC) high-level specification in + the RISC-V Privileged Architecture specification. The PLIC connects all + external interrupts in the system to all hart contexts in the system, via + the external interrupt source in each hart. A hart context is a privilege mode in a hardware execution thread. For example, in an 4 core system with 2-way SMT, you have 8 harts and probably at least two @@ -41,9 +42,14 @@ maintainers: properties: compatible: - items: - - const: sifive,fu540-c000-plic - - const: sifive,plic-1.0.0 + oneOf: + - items: + - const: sifive,fu540-c000-plic + - const: sifive,plic-1.0.0 + + - items: + - const: canaan,k210-plic + - const: sifive,plic-1.0.0 reg: maxItems: 1