| Message ID | 20210920132559.151678-1-krzysztof.kozlowski@canonical.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [RESEND] dt-bindings: riscv: correct e51 and u54-mc CPU bindings | expand |
On Mon, 20 Sep 2021 15:25:59 +0200, Krzysztof Kozlowski wrote: > All existing boards with sifive,e51 and sifive,u54-mc use it on top of > sifive,rocket0 compatible: > > arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: cpu@0: compatible: 'oneOf' conditional failed, one must be fixed: > ['sifive,e51', 'sifive,rocket0', 'riscv'] is too long > Additional items are not allowed ('riscv' was unexpected) > Additional items are not allowed ('sifive,rocket0', 'riscv' were unexpected) > 'riscv' was expected > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > > --- > > Hi Rob, > > You previously acked this patch but I think it will be easier if you > take it directly. > > Best regards, > Krzysztof > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > Applied, thanks!
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index e534f6a7cfa1..aa5fb64d57eb 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -31,9 +31,7 @@ properties: - sifive,bullet0 - sifive,e5 - sifive,e7 - - sifive,e51 - sifive,e71 - - sifive,u54-mc - sifive,u74-mc - sifive,u54 - sifive,u74 @@ -41,6 +39,12 @@ properties: - sifive,u7 - canaan,k210 - const: riscv + - items: + - enum: + - sifive,e51 + - sifive,u54-mc + - const: sifive,rocket0 + - const: riscv - const: riscv # Simulator only description: Identifies that the hart uses the RISC-V instruction set
All existing boards with sifive,e51 and sifive,u54-mc use it on top of sifive,rocket0 compatible: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: cpu@0: compatible: 'oneOf' conditional failed, one must be fixed: ['sifive,e51', 'sifive,rocket0', 'riscv'] is too long Additional items are not allowed ('riscv' was unexpected) Additional items are not allowed ('sifive,rocket0', 'riscv' were unexpected) 'riscv' was expected Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> --- Hi Rob, You previously acked this patch but I think it will be easier if you take it directly. Best regards, Krzysztof --- Documentation/devicetree/bindings/riscv/cpus.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)