| Message ID | 20210927005115.610264-1-wcohen@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | perf annotate: Add riscv64 support | expand |
Em Sun, Sep 26, 2021 at 08:51:15PM -0400, William Cohen escreveu: > This patch adds basic arch initialization and instruction associate > support for the riscv64 CPU architecture. > > Example output: > > $ perf annotate --stdio2 > Samples: 122K of event 'task-clock:u', 4000 Hz, Event count (approx.): 30637250000, [percent: local period] > strcmp() /usr/lib64/libc-2.32.so > Percent > > Disassembly of section .text: > > 0000000000069a30 <strcmp>: > __GI_strcmp(): > const unsigned char *s2 = (const unsigned char *) p2; > unsigned char c1, c2; > > do > { > c1 = (unsigned char) *s1++; > 37.30 lbu a5,0(a0) > c2 = (unsigned char) *s2++; > 1.23 addi a1,a1,1 > c1 = (unsigned char) *s1++; > 18.68 addi a0,a0,1 > c2 = (unsigned char) *s2++; > 1.37 lbu a4,-1(a1) > if (c1 == '\0') > 18.71 ↓ beqz a5,18 > return c1 - c2; > } Thanks, applied. - Arnaldo > Signed-off-by: William Cohen <wcohen@redhat.com> > --- > .../perf/arch/riscv64/annotate/instructions.c | 34 +++++++++++++++++++ > tools/perf/util/annotate.c | 5 +++ > 2 files changed, 39 insertions(+) > create mode 100644 tools/perf/arch/riscv64/annotate/instructions.c > > diff --git a/tools/perf/arch/riscv64/annotate/instructions.c b/tools/perf/arch/riscv64/annotate/instructions.c > new file mode 100644 > index 000000000000..869a0eb28953 > --- /dev/null > +++ b/tools/perf/arch/riscv64/annotate/instructions.c > @@ -0,0 +1,34 @@ > +// SPDX-License-Identifier: GPL-2.0 > + > +static > +struct ins_ops *riscv64__associate_ins_ops(struct arch *arch, const char *name) > +{ > + struct ins_ops *ops = NULL; > + > + if (!strncmp(name, "jal", 3) || > + !strncmp(name, "jr", 2) || > + !strncmp(name, "call", 4)) > + ops = &call_ops; > + else if (!strncmp(name, "ret", 3)) > + ops = &ret_ops; > + else if (name[0] == 'j' || name[0] == 'b') > + ops = &jump_ops; > + else > + return NULL; > + > + arch__associate_ins_ops(arch, name, ops); > + > + return ops; > +} > + > +static > +int riscv64__annotate_init(struct arch *arch, char *cpuid __maybe_unused) > +{ > + if (!arch->initialized) { > + arch->associate_instruction_ops = riscv64__associate_ins_ops; > + arch->initialized = true; > + arch->objdump.comment_char = '#'; > + } > + > + return 0; > +} > diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c > index 0bae061b2d6d..d919fa993872 100644 > --- a/tools/perf/util/annotate.c > +++ b/tools/perf/util/annotate.c > @@ -151,6 +151,7 @@ static int arch__associate_ins_ops(struct arch* arch, const char *name, struct i > #include "arch/mips/annotate/instructions.c" > #include "arch/x86/annotate/instructions.c" > #include "arch/powerpc/annotate/instructions.c" > +#include "arch/riscv64/annotate/instructions.c" > #include "arch/s390/annotate/instructions.c" > #include "arch/sparc/annotate/instructions.c" > > @@ -192,6 +193,10 @@ static struct arch architectures[] = { > .name = "powerpc", > .init = powerpc__annotate_init, > }, > + { > + .name = "riscv64", > + .init = riscv64__annotate_init, > + }, > { > .name = "s390", > .init = s390__annotate_init, > -- > 2.27.0
diff --git a/tools/perf/arch/riscv64/annotate/instructions.c b/tools/perf/arch/riscv64/annotate/instructions.c new file mode 100644 index 000000000000..869a0eb28953 --- /dev/null +++ b/tools/perf/arch/riscv64/annotate/instructions.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 + +static +struct ins_ops *riscv64__associate_ins_ops(struct arch *arch, const char *name) +{ + struct ins_ops *ops = NULL; + + if (!strncmp(name, "jal", 3) || + !strncmp(name, "jr", 2) || + !strncmp(name, "call", 4)) + ops = &call_ops; + else if (!strncmp(name, "ret", 3)) + ops = &ret_ops; + else if (name[0] == 'j' || name[0] == 'b') + ops = &jump_ops; + else + return NULL; + + arch__associate_ins_ops(arch, name, ops); + + return ops; +} + +static +int riscv64__annotate_init(struct arch *arch, char *cpuid __maybe_unused) +{ + if (!arch->initialized) { + arch->associate_instruction_ops = riscv64__associate_ins_ops; + arch->initialized = true; + arch->objdump.comment_char = '#'; + } + + return 0; +} diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index 0bae061b2d6d..d919fa993872 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -151,6 +151,7 @@ static int arch__associate_ins_ops(struct arch* arch, const char *name, struct i #include "arch/mips/annotate/instructions.c" #include "arch/x86/annotate/instructions.c" #include "arch/powerpc/annotate/instructions.c" +#include "arch/riscv64/annotate/instructions.c" #include "arch/s390/annotate/instructions.c" #include "arch/sparc/annotate/instructions.c" @@ -192,6 +193,10 @@ static struct arch architectures[] = { .name = "powerpc", .init = powerpc__annotate_init, }, + { + .name = "riscv64", + .init = riscv64__annotate_init, + }, { .name = "s390", .init = s390__annotate_init,
This patch adds basic arch initialization and instruction associate support for the riscv64 CPU architecture. Example output: $ perf annotate --stdio2 Samples: 122K of event 'task-clock:u', 4000 Hz, Event count (approx.): 30637250000, [percent: local period] strcmp() /usr/lib64/libc-2.32.so Percent Disassembly of section .text: 0000000000069a30 <strcmp>: __GI_strcmp(): const unsigned char *s2 = (const unsigned char *) p2; unsigned char c1, c2; do { c1 = (unsigned char) *s1++; 37.30 lbu a5,0(a0) c2 = (unsigned char) *s2++; 1.23 addi a1,a1,1 c1 = (unsigned char) *s1++; 18.68 addi a0,a0,1 c2 = (unsigned char) *s2++; 1.37 lbu a4,-1(a1) if (c1 == '\0') 18.71 ↓ beqz a5,18 return c1 - c2; } Signed-off-by: William Cohen <wcohen@redhat.com> --- .../perf/arch/riscv64/annotate/instructions.c | 34 +++++++++++++++++++ tools/perf/util/annotate.c | 5 +++ 2 files changed, 39 insertions(+) create mode 100644 tools/perf/arch/riscv64/annotate/instructions.c