diff mbox series

riscv: fix misalgned trap vector base address

Message ID 20211018052238.522905-1-181250012@smail.nju.edu.cn (mailing list archive)
State New, archived
Headers show
Series riscv: fix misalgned trap vector base address | expand

Commit Message

Chen Lu Oct. 18, 2021, 5:22 a.m. UTC
* The trap vector marked by label .Lsecondary_park should align on a
  4-byte boundary. If not, CSR_TVEC may be set to an incorrect address.
* This bug is introduced at commit e011995e826f8 ("RISC-V: Move relocate
  and few other functions out of __init").
* This bug is exposed with an educational emualtor.

Signed-off-by: Chen Lu <181250012@smail.nju.edu.cn>
---
 arch/riscv/kernel/head.S | 1 +
 1 file changed, 1 insertion(+)

Comments

Anup Patel Oct. 18, 2021, 5:31 a.m. UTC | #1
On Mon, Oct 18, 2021 at 10:52 AM Chen Lu <181250012@smail.nju.edu.cn> wrote:
>
> * The trap vector marked by label .Lsecondary_park should align on a
>   4-byte boundary. If not, CSR_TVEC may be set to an incorrect address.
> * This bug is introduced at commit e011995e826f8 ("RISC-V: Move relocate
>   and few other functions out of __init").
> * This bug is exposed with an educational emualtor.
>

Please add "Fixes:" line here.

> Signed-off-by: Chen Lu <181250012@smail.nju.edu.cn>

Otherwise it looks good to me.

Reviewed-by: Anup Patel <anup.patel@wdc.com>

Regards,
Anup

> ---
>  arch/riscv/kernel/head.S | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index fce5184b22c3..52c5ff9804c5 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -193,6 +193,7 @@ setup_trap_vector:
>         csrw CSR_SCRATCH, zero
>         ret
>
> +.align 2
>  .Lsecondary_park:
>         /* We lack SMP support or have too many harts, so park this hart */
>         wfi
> --
> 2.30.2
>
>
>
Palmer Dabbelt Oct. 27, 2021, 9:22 p.m. UTC | #2
On Sun, 17 Oct 2021 22:22:38 PDT (-0700), 181250012@smail.nju.edu.cn wrote:
> * The trap vector marked by label .Lsecondary_park should align on a
>   4-byte boundary. If not, CSR_TVEC may be set to an incorrect address.
> * This bug is introduced at commit e011995e826f8 ("RISC-V: Move relocate
>   and few other functions out of __init").
> * This bug is exposed with an educational emualtor.
>
> Signed-off-by: Chen Lu <181250012@smail.nju.edu.cn>
> ---
>  arch/riscv/kernel/head.S | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index fce5184b22c3..52c5ff9804c5 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -193,6 +193,7 @@ setup_trap_vector:
>  	csrw CSR_SCRATCH, zero
>  	ret
>
> +.align 2
>  .Lsecondary_park:
>  	/* We lack SMP support or have too many harts, so park this hart */
>  	wfi

Thanks, this is on fixes (with some commit message cleanups).
diff mbox series

Patch

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index fce5184b22c3..52c5ff9804c5 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -193,6 +193,7 @@  setup_trap_vector:
 	csrw CSR_SCRATCH, zero
 	ret
 
+.align 2
 .Lsecondary_park:
 	/* We lack SMP support or have too many harts, so park this hart */
 	wfi