@@ -50,6 +50,7 @@ struct dw8250_data {
struct reset_control *rst;
unsigned int skip_autocfg:1;
+ unsigned int skip_clk_set_rate:1;
unsigned int uart_16550_compatible:1;
};
@@ -326,14 +327,18 @@ dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
pm_runtime_put_sync_suspend(port->dev);
}
-static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
- struct ktermios *old)
+static void dw8250_do_clk_set_rate(struct uart_port *p, struct ktermios *termios)
{
- unsigned long newrate = tty_termios_baud_rate(termios) * 16;
struct dw8250_data *d = to_dw8250_data(p->private_data);
+ unsigned long newrate;
long rate;
int ret;
+ if (d->skip_clk_set_rate)
+ return;
+
+ newrate = tty_termios_baud_rate(termios) * 16;
+
clk_disable_unprepare(d->clk);
rate = clk_round_rate(d->clk, newrate);
if (rate > 0) {
@@ -349,7 +354,12 @@ static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
swap(p->uartclk, rate);
}
clk_prepare_enable(d->clk);
+}
+static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
+ struct ktermios *old)
+{
+ dw8250_do_clk_set_rate(p, termios);
dw8250_do_set_termios(p, termios, old);
}
@@ -417,6 +427,8 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
if (of_device_is_compatible(np, "marvell,armada-38x-uart"))
p->serial_out = dw8250_serial_out38x;
+ if (of_device_is_compatible(np, "starfive,jh7100-uart"))
+ data->skip_clk_set_rate = true;
} else if (acpi_dev_present("APMC0D08", NULL, -1)) {
p->iotype = UPIO_MEM32;
@@ -699,6 +711,7 @@ static const struct of_device_id dw8250_of_match[] = {
{ .compatible = "cavium,octeon-3860-uart" },
{ .compatible = "marvell,armada-38x-uart" },
{ .compatible = "renesas,rzn1-uart" },
+ { .compatible = "starfive,jh7100-uart" },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dw8250_of_match);
On the StarFive JH7100 SoC the UART core clocks can't be set to exactly 16 * 115200Hz and many other common bitrates. Trying this will only result in a higher input clock, but low enough that the UART's internal divisor can't come close enough to the baud rate target. So rather than try to set the input clock it's better to rely solely on the UART's internal divisor. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> --- drivers/tty/serial/8250/8250_dw.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-)