new file mode 100644
@@ -0,0 +1,14 @@
+# Format:
+# MIDR,Version,JSON/file/pathname,Type
+#
+# where
+# MIDR Processor version
+# Variant[23:20] and Revision [3:0] should be zero.
+# Version could be used to track version of JSON file
+# but currently unused.
+# JSON/file/pathname is the path to JSON file, relative
+# to tools/perf/pmu-events/arch/riscv/.
+# Type is core, uncore etc
+#
+#
+#Family-model,Version,Filename,EventType
new file mode 100644
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+[
+ {
+ "PublicDescription": "CPU Cycles",
+ "EventCode": "0x00",
+ "EventName": "riscv_cycles",
+ "BriefDescription": "CPU cycles RISC-V generic counter"
+ },
+ {
+ "PublicDescription": "CPU Time",
+ "EventCode": "0x01",
+ "EventName": "riscv_time",
+ "BriefDescription": "CPU time RISC-V generic counter"
+ },
+ {
+ "PublicDescription": "CPU Instructions",
+ "EventCode": "0x02",
+ "EventName": "riscv_instret",
+ "BriefDescription": "CPU retired instructions RISC-V generic counter"
+ }
+]
\ No newline at end of file
The pmu-events now supports custom events for RISC-V, plus the cycle, time and instret events were defined. Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt> --- tools/perf/pmu-events/arch/riscv/mapfile.csv | 14 +++++++++++++ .../pmu-events/arch/riscv/riscv-generic.json | 20 +++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json