| Message ID | 20220126171442.1338740-1-aurelien@aurel32.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: fix build with binutils 2.38 | expand |
Hi Aurelien, On Wed, Jan 26, 2022 at 6:41 PM Aurelien Jarno <aurelien@aurel32.net> wrote: > > From version 2.38, binutils default to ISA spec version 20191213. This > means that the csr read/write (csrr*/csrw*) instructions and fence.i > instruction has separated from the `I` extension, become two standalone > extensions: Zicsr and Zifencei. As the kernel uses those instruction, > this causes the following build failure: > > CC arch/riscv/kernel/vdso/vgettimeofday.o > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages: > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > The fix is to specify those extensions explicitely in -march. However as > older binutils version do not support this, we first need to detect > that. > > Cc: stable@vger.kernel.org # 4.15+ > Cc: Kito Cheng <kito.cheng@gmail.com> > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > --- > arch/riscv/Makefile | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > index 8a107ed18b0d..7d81102cffd4 100644 > --- a/arch/riscv/Makefile > +++ b/arch/riscv/Makefile > @@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima > riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima > riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd > riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > + > +# Newer binutils versions default to ISA spec version 20191213 which moves some > +# instructions from the I extension to the Zicsr and Zifencei extensions. > +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) > +riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei > + > KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) > KBUILD_AFLAGS += -march=$(riscv-march-y) > > -- > 2.34.1 > > That fixes our kernel build with the new binutils, so you can add: Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> Thanks for working on this! Alex > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, 26 Jan 2022 09:14:42 PST (-0800), aurelien@aurel32.net wrote: > From version 2.38, binutils default to ISA spec version 20191213. This > means that the csr read/write (csrr*/csrw*) instructions and fence.i > instruction has separated from the `I` extension, become two standalone > extensions: Zicsr and Zifencei. As the kernel uses those instruction, > this causes the following build failure: > > CC arch/riscv/kernel/vdso/vgettimeofday.o > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages: > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > The fix is to specify those extensions explicitely in -march. However as > older binutils version do not support this, we first need to detect > that. > > Cc: stable@vger.kernel.org # 4.15+ > Cc: Kito Cheng <kito.cheng@gmail.com> > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > --- > arch/riscv/Makefile | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > index 8a107ed18b0d..7d81102cffd4 100644 > --- a/arch/riscv/Makefile > +++ b/arch/riscv/Makefile > @@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima > riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima > riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd > riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > + > +# Newer binutils versions default to ISA spec version 20191213 which moves some > +# instructions from the I extension to the Zicsr and Zifencei extensions. > +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) > +riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei > + > KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) > KBUILD_AFLAGS += -march=$(riscv-march-y) Thanks, this is on fixes. It's CC stable, but doesn't have a "Fixes" tag -- I did that on purpose as this isn't really fixing a bug in Linux so I'm not sure it's right to point at a particular patch, but I'm not sure how that will play with the stable tree.
On Thu, Feb 10, 2022 at 09:40:22AM -0800, Palmer Dabbelt wrote: > On Wed, 26 Jan 2022 09:14:42 PST (-0800), aurelien@aurel32.net wrote: > > From version 2.38, binutils default to ISA spec version 20191213. This > > means that the csr read/write (csrr*/csrw*) instructions and fence.i > > instruction has separated from the `I` extension, become two standalone > > extensions: Zicsr and Zifencei. As the kernel uses those instruction, > > this causes the following build failure: > > > > CC arch/riscv/kernel/vdso/vgettimeofday.o > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages: > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > > > The fix is to specify those extensions explicitely in -march. However as > > older binutils version do not support this, we first need to detect > > that. > > > > Cc: stable@vger.kernel.org # 4.15+ > > Cc: Kito Cheng <kito.cheng@gmail.com> > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > > --- > > arch/riscv/Makefile | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > > index 8a107ed18b0d..7d81102cffd4 100644 > > --- a/arch/riscv/Makefile > > +++ b/arch/riscv/Makefile > > @@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima > > riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima > > riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd > > riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > > + > > +# Newer binutils versions default to ISA spec version 20191213 which moves some > > +# instructions from the I extension to the Zicsr and Zifencei extensions. > > +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) > > +riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei > > + > > KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) > > KBUILD_AFLAGS += -march=$(riscv-march-y) > > Thanks, this is on fixes. It's CC stable, but doesn't have a "Fixes" tag -- > I did that on purpose as this isn't really fixing a bug in Linux so I'm not > sure it's right to point at a particular patch, but I'm not sure how that > will play with the stable tree. I will backport it as far back as it easily goes to, and then forget about it :) If you have a Fixes: tag, and it doesn't properly backport that far, then you will get a "FAILED:" email notifying you about it. hope that helps explain things, greg k-h
On 26.01.2022 18:14:42, Aurelien Jarno wrote: > From version 2.38, binutils default to ISA spec version 20191213. This > means that the csr read/write (csrr*/csrw*) instructions and fence.i > instruction has separated from the `I` extension, become two standalone > extensions: Zicsr and Zifencei. As the kernel uses those instruction, > this causes the following build failure: > > CC arch/riscv/kernel/vdso/vgettimeofday.o > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages: > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > The fix is to specify those extensions explicitely in -march. However as > older binutils version do not support this, we first need to detect > that. > > Cc: stable@vger.kernel.org # 4.15+ > Cc: Kito Cheng <kito.cheng@gmail.com> > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > --- > arch/riscv/Makefile | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > index 8a107ed18b0d..7d81102cffd4 100644 > --- a/arch/riscv/Makefile > +++ b/arch/riscv/Makefile > @@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima > riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima > riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd > riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > + > +# Newer binutils versions default to ISA spec version 20191213 which moves some > +# instructions from the I extension to the Zicsr and Zifencei extensions. > +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) > +riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei > + > KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) > KBUILD_AFLAGS += -march=$(riscv-march-y) I'm on current linus/master, this change breaks on current Debian testing with: | make: Leaving directory 'linux' | SYNC include/config/auto.conf.cmd | GEN Makefile | GEN Makefile | CC scripts/mod/empty.o | CHECK linux/scripts/mod/empty.c | invalid argument to '-march': '_zicsr_zifencei' Used components: | $ riscv64-linux-gnu-gcc -v | Using built-in specs. | COLLECT_GCC=/usr/bin/riscv64-linux-gnu-gcc | COLLECT_LTO_WRAPPER=/usr/lib/gcc-cross/riscv64-linux-gnu/11/lto-wrapper | Target: riscv64-linux-gnu | Configured with: ../src/configure -v --with-pkgversion='Debian 11.2.0-9' --with-bugurl=file:///usr/share/doc/gcc-11/README.Bugs --enable-languages=c,ada,c++,go,d,fortran,objc,obj-c++,m2 --prefix=/usr --with-gcc-major-version-only --program-suffix=-11 --enable-shared --enable-linker-build-id --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --libdir=/usr/lib --enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --with-default-libstdcxx-abi=new --enable-gnu-unique-object --disable-libitm --disable-libquadmath --disable-libquadmath-support --enable-plugin --enable-default-pie --with-system-zlib --enable-libphobos-checking=release --without-target-system-zlib --enable-multiarch --disable-werror --disable-multilib --with-arch=rv64imafdc --with-abi=lp64d --enable-checking=release --build=x86_64-linux-gnu --host=x86_64-linux-gnu --target=riscv64-linux-gnu --program-prefix=riscv64-linux-gnu- --includedir=/usr/riscv64-linux-gnu/include --with-build-config=bootstrap-lto-lean --enable-link-serialization=2 | Thread model: posix | Supported LTO compression algorithms: zlib zstd | gcc version 11.2.0 (Debian 11.2.0-9) | $ riscv64-linux-gnu-ld -v | GNU ld (GNU Binutils for Debian) 2.38 regards, Marc
On 31.03.2022 12:32:47, Marc Kleine-Budde wrote: > On 26.01.2022 18:14:42, Aurelien Jarno wrote: > > From version 2.38, binutils default to ISA spec version 20191213. This > > means that the csr read/write (csrr*/csrw*) instructions and fence.i > > instruction has separated from the `I` extension, become two standalone > > extensions: Zicsr and Zifencei. As the kernel uses those instruction, > > this causes the following build failure: > > > > CC arch/riscv/kernel/vdso/vgettimeofday.o > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages: > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > > > The fix is to specify those extensions explicitely in -march. However as > > older binutils version do not support this, we first need to detect > > that. > > > > Cc: stable@vger.kernel.org # 4.15+ > > Cc: Kito Cheng <kito.cheng@gmail.com> > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > > --- > > arch/riscv/Makefile | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > > index 8a107ed18b0d..7d81102cffd4 100644 > > --- a/arch/riscv/Makefile > > +++ b/arch/riscv/Makefile > > @@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima > > riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima > > riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd > > riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > > + > > +# Newer binutils versions default to ISA spec version 20191213 which moves some > > +# instructions from the I extension to the Zicsr and Zifencei extensions. > > +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) > > +riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei > > + > > KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) > > KBUILD_AFLAGS += -march=$(riscv-march-y) > > I'm on current linus/master, this change breaks on current Debian > testing with: > > | make: Leaving directory 'linux' > | SYNC include/config/auto.conf.cmd > | GEN Makefile > | GEN Makefile > | CC scripts/mod/empty.o > | CHECK linux/scripts/mod/empty.c ^^^^^ It's actually "sparse" that breaks > | invalid argument to '-march': '_zicsr_zifencei' | $ sparse --version | 0.6.4 (Debian: 0.6.4-2) Compiling without "C=1" for now. regards, Marc
Cc += linux-sparse, Uwe, Luc Van Oostenryck tl;dr: A recent change in the kernel regarding the riscv -march handling breaks current sparse. On 31.03.2022 12:39:14, Marc Kleine-Budde wrote: > On 31.03.2022 12:32:47, Marc Kleine-Budde wrote: > > On 26.01.2022 18:14:42, Aurelien Jarno wrote: > > > From version 2.38, binutils default to ISA spec version 20191213. This > > > means that the csr read/write (csrr*/csrw*) instructions and fence.i > > > instruction has separated from the `I` extension, become two standalone > > > extensions: Zicsr and Zifencei. As the kernel uses those instruction, > > > this causes the following build failure: > > > > > > CC arch/riscv/kernel/vdso/vgettimeofday.o > > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages: > > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > > > > > The fix is to specify those extensions explicitely in -march. However as > > > older binutils version do not support this, we first need to detect > > > that. > > > > > > Cc: stable@vger.kernel.org # 4.15+ > > > Cc: Kito Cheng <kito.cheng@gmail.com> > > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > > > --- > > > arch/riscv/Makefile | 6 ++++++ > > > 1 file changed, 6 insertions(+) > > > > > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > > > index 8a107ed18b0d..7d81102cffd4 100644 > > > --- a/arch/riscv/Makefile > > > +++ b/arch/riscv/Makefile > > > @@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima > > > riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima > > > riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd > > > riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > > > + > > > +# Newer binutils versions default to ISA spec version 20191213 which moves some > > > +# instructions from the I extension to the Zicsr and Zifencei extensions. > > > +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) > > > +riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei > > > + > > > KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) > > > KBUILD_AFLAGS += -march=$(riscv-march-y) > > > > I'm on current linus/master, this change breaks on current Debian > > testing with: > > > > | make: Leaving directory 'linux' > > | SYNC include/config/auto.conf.cmd > > | GEN Makefile > > | GEN Makefile > > | CC scripts/mod/empty.o > > | CHECK linux/scripts/mod/empty.c > ^^^^^ > It's actually "sparse" that breaks > > > | invalid argument to '-march': '_zicsr_zifencei' > > | $ sparse --version > | 0.6.4 (Debian: 0.6.4-2) regards, Marc
Hi, On 2022-03-31 12:51, Marc Kleine-Budde wrote: > Cc += linux-sparse, Uwe, Luc Van Oostenryck > > tl;dr: > > A recent change in the kernel regarding the riscv -march handling breaks > current sparse. > > On 31.03.2022 12:39:14, Marc Kleine-Budde wrote: > > On 31.03.2022 12:32:47, Marc Kleine-Budde wrote: > > > On 26.01.2022 18:14:42, Aurelien Jarno wrote: > > > > From version 2.38, binutils default to ISA spec version 20191213. This > > > > means that the csr read/write (csrr*/csrw*) instructions and fence.i > > > > instruction has separated from the `I` extension, become two standalone > > > > extensions: Zicsr and Zifencei. As the kernel uses those instruction, > > > > this causes the following build failure: > > > > > > > > CC arch/riscv/kernel/vdso/vgettimeofday.o > > > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages: > > > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > > > <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > > > > > > > > The fix is to specify those extensions explicitely in -march. However as > > > > older binutils version do not support this, we first need to detect > > > > that. > > > > > > > > Cc: stable@vger.kernel.org # 4.15+ > > > > Cc: Kito Cheng <kito.cheng@gmail.com> > > > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > > > > --- > > > > arch/riscv/Makefile | 6 ++++++ > > > > 1 file changed, 6 insertions(+) > > > > > > > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > > > > index 8a107ed18b0d..7d81102cffd4 100644 > > > > --- a/arch/riscv/Makefile > > > > +++ b/arch/riscv/Makefile > > > > @@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima > > > > riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima > > > > riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd > > > > riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > > > > + > > > > +# Newer binutils versions default to ISA spec version 20191213 which moves some > > > > +# instructions from the I extension to the Zicsr and Zifencei extensions. > > > > +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) > > > > +riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei > > > > + > > > > KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) > > > > KBUILD_AFLAGS += -march=$(riscv-march-y) > > > > > > I'm on current linus/master, this change breaks on current Debian > > > testing with: > > > > > > | make: Leaving directory 'linux' > > > | SYNC include/config/auto.conf.cmd > > > | GEN Makefile > > > | GEN Makefile > > > | CC scripts/mod/empty.o > > > | CHECK linux/scripts/mod/empty.c > > ^^^^^ > > It's actually "sparse" that breaks > > > > > | invalid argument to '-march': '_zicsr_zifencei' > > > > | $ sparse --version > > | 0.6.4 (Debian: 0.6.4-2) I confirm the issue. To make things clear, it's not a Makefile issue, sparse get passed the correct -march=rv64ima_zicsr_zifencei value, and only display the part it can't parse. On the medium/long term, sparse should get fixed to support those extensions. On the short term, we need to find a way to get different flags for sparse than for as/gcc.
On Thu, Mar 31, 2022 at 3:51 AM Marc Kleine-Budde <mkl@pengutronix.de> wrote: > > Cc += linux-sparse, Uwe, Luc Van Oostenryck > > tl;dr: > > A recent change in the kernel regarding the riscv -march handling breaks > current sparse. Gaah. Normally sparse doesn't even look at the -march flag, but for riscv it does, because it's meaningful for the predefined macros. Maybe that 'die()' shouldn't be so fatal. And maybe add a few more extensions (but ignore them) to the parsing. Something ENTIRELY UNTESTED like the attached. Linus
On Thu, 31 Mar 2022 11:16:53 PDT (-0700), Linus Torvalds wrote: > On Thu, Mar 31, 2022 at 3:51 AM Marc Kleine-Budde <mkl@pengutronix.de> wrote: >> >> Cc += linux-sparse, Uwe, Luc Van Oostenryck >> >> tl;dr: >> >> A recent change in the kernel regarding the riscv -march handling breaks >> current sparse. Sorry about that, looks like I'm not running sparse as part of my testing. I'll add it, but it might take a bit as I'm assuming there will be a bunch of issues it points out. > Gaah. Normally sparse doesn't even look at the -march flag, but for > riscv it does, because it's meaningful for the predefined macros. > > Maybe that 'die()' shouldn't be so fatal. And maybe add a few more > extensions (but ignore them) to the parsing. > > Something ENTIRELY UNTESTED like the attached. Converting this to a warning seems reasonable to me, as then we're not as coupled to the sparse version. The current crop of extensions don't set anything exciting for Linux, but there are some on the horizon that likely will -- hopefully having sparse in my test setup should be sufficient to dig those up, though. As far as the new extension go: "Counters" isn't an ISA extension, and "e" defines "__riscv_32e". It'd also be slightly saner to match on "_Zifencei", but that probably doesn't matter (GCC is sufficiently strict here). Looks like there's also some oddities in the sparse ISA string parsing, I'll go clean them up as I get it running locally. We could also stop relying on the compiler's defines, which would avoid this problem entirely, but IIRC that was discussed when decided to modify sparse in the first place and we went this way (though I don't remember why). That would keep everything inside the kernel.
On 31.03.2022 11:16:53, Linus Torvalds wrote: > On Thu, Mar 31, 2022 at 3:51 AM Marc Kleine-Budde <mkl@pengutronix.de> wrote: > > > > Cc += linux-sparse, Uwe, Luc Van Oostenryck > > > > tl;dr: > > > > A recent change in the kernel regarding the riscv -march handling breaks > > current sparse. > > Gaah. Normally sparse doesn't even look at the -march flag, but for > riscv it does, because it's meaningful for the predefined macros. > > Maybe that 'die()' shouldn't be so fatal. And maybe add a few more > extensions (but ignore them) to the parsing. > > Something ENTIRELY UNTESTED like the attached. Works-for-me: | CHECK /srv/work/frogger/socketcan/linux/drivers/net/can/usb/etas_es58x/es58x_core.c | WARNING: invalid argument to '-march': 'zicsr_zifencei' Tested-by: Marc Kleine-Budde <mkl@pengutronix.de> Regards, Marc
On Thu, Mar 31, 2022 at 11:53 PM Marc Kleine-Budde <mkl@pengutronix.de> wrote: > > | WARNING: invalid argument to '-march': 'zicsr_zifencei' Gaah, it works but still warns because I cut-and-pasted those zicsr/zifencei options from some random source that had them capitalized and I didn't look closely enough at the reports. Anyway, hopefully somebody can bother to fix up that. Possibly by changing the strncmp to a strnicmp - but I don't know what the rules for lower-case vs capitals are for the other options. I'm still busy with the kernel merge window, so this gets archived on my side.. Linus
On Fri, 01 Apr 2022 10:14:03 PDT (-0700), Linus Torvalds wrote: > On Thu, Mar 31, 2022 at 11:53 PM Marc Kleine-Budde <mkl@pengutronix.de> wrote: >> >> | WARNING: invalid argument to '-march': 'zicsr_zifencei' > > Gaah, it works but still warns because I cut-and-pasted those > zicsr/zifencei options from some random source that had them > capitalized and I didn't look closely enough at the reports. > > Anyway, hopefully somebody can bother to fix up that. Possibly by > changing the strncmp to a strnicmp - but I don't know what the rules > for lower-case vs capitals are for the other options. I'm still busy > with the kernel merge window, so this gets archived on my side.. I'm gluing sparse to my build tests now, so I'll sort it out (that'll also make sure a failure doesn't leak again). Might not be today, but shouldn't take too long.
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 8a107ed18b0d..7d81102cffd4 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c + +# Newer binutils versions default to ISA spec version 20191213 which moves some +# instructions from the I extension to the Zicsr and Zifencei extensions. +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) +riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei + KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) KBUILD_AFLAGS += -march=$(riscv-march-y)
From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure: CC arch/riscv/kernel/vdso/vgettimeofday.o <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages: <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' The fix is to specify those extensions explicitely in -march. However as older binutils version do not support this, we first need to detect that. Cc: stable@vger.kernel.org # 4.15+ Cc: Kito Cheng <kito.cheng@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- arch/riscv/Makefile | 6 ++++++ 1 file changed, 6 insertions(+)