| Message ID | 20220215090211.911366-2-atishp@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Provide a fraemework for RISC-V ISA extensions | expand |
On Tue, Feb 15, 2022 at 2:32 PM Atish Patra <atishp@rivosinc.com> wrote: > > From: Tsukasa OI <research_trasio@irq.a4lg.com> > > This commit replaces BITS_PER_LONG with number of alphabet letters. > > Current ISA pretty-printing code expects extension 'a' (bit 0) through > 'z' (bit 25). Although bit 26 and higher is not currently used (thus never > cause an issue in practice), it will be an annoying problem if we start to > use those in the future. > > This commit disables printing high bits for now. > > Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> > Signed-off-by: Atish Patra <atishp@rivosinc.com> > Tested-by: Heiko Stuebner <heiko@sntech.de> Looks good to me. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup > --- > arch/riscv/kernel/cpufeature.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index d959d207a40d..dd3d57eb4eea 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -13,6 +13,8 @@ > #include <asm/smp.h> > #include <asm/switch_to.h> > > +#define NUM_ALPHA_EXTS ('z' - 'a' + 1) > + > unsigned long elf_hwcap __read_mostly; > > /* Host ISA bitmap */ > @@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void) > { > struct device_node *node; > const char *isa; > - char print_str[BITS_PER_LONG + 1]; > + char print_str[NUM_ALPHA_EXTS + 1]; > size_t i, j, isa_len; > static unsigned long isa2hwcap[256] = {0}; > > @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void) > } > > memset(print_str, 0, sizeof(print_str)); > - for (i = 0, j = 0; i < BITS_PER_LONG; i++) > + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) > if (riscv_isa[0] & BIT_MASK(i)) > print_str[j++] = (char)('a' + i); > pr_info("riscv: ISA extensions %s\n", print_str); > > memset(print_str, 0, sizeof(print_str)); > - for (i = 0, j = 0; i < BITS_PER_LONG; i++) > + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) > if (elf_hwcap & BIT_MASK(i)) > print_str[j++] = (char)('a' + i); > pr_info("riscv: ELF capabilities %s\n", print_str); > -- > 2.30.2 >
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d959d207a40d..dd3d57eb4eea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -13,6 +13,8 @@ #include <asm/smp.h> #include <asm/switch_to.h> +#define NUM_ALPHA_EXTS ('z' - 'a' + 1) + unsigned long elf_hwcap __read_mostly; /* Host ISA bitmap */ @@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - char print_str[BITS_PER_LONG + 1]; + char print_str[NUM_ALPHA_EXTS + 1]; size_t i, j, isa_len; static unsigned long isa2hwcap[256] = {0}; @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void) } memset(print_str, 0, sizeof(print_str)); - for (i = 0, j = 0; i < BITS_PER_LONG; i++) + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] = (char)('a' + i); pr_info("riscv: ISA extensions %s\n", print_str); memset(print_str, 0, sizeof(print_str)); - for (i = 0, j = 0; i < BITS_PER_LONG; i++) + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (elf_hwcap & BIT_MASK(i)) print_str[j++] = (char)('a' + i); pr_info("riscv: ELF capabilities %s\n", print_str);