| Message ID | 20220710111330.3920699-3-mail@conchuod.ie (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | JH7100 Monitor Core | expand |
On Sun, 10 Jul 2022 at 13:13, Conor Dooley <mail@conchuod.ie> wrote: > > From: Conor Dooley <conor.dooley@microchip.com> > > The JH7100 has a 32 bit monitor core that is missing from the device > tree. Add it (and its cpu-map entry) to more accurately reflect the > actual topology of the SoC. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/boot/dts/starfive/jh7100.dtsi | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi > index c617a61e26e2..840875fcb633 100644 > --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi > @@ -67,6 +67,22 @@ cpu1_intc: interrupt-controller { > }; > }; > > + E24: cpu@2 { > + compatible = "sifive,e24", "riscv"; > + device_type = "cpu"; > + i-cache-block-size = <32>; > + i-cache-sets = <256>; > + i-cache-size = <16384>; > + reg = <0x2>; > + riscv,isa = "rv32imafc"; > + status = "disabled"; > + cpu2_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; Maybe you could make this look a bit more like the nodes above, so compatible reg <the rest sorted> <blank line> cpu2_intc: interrupt-controller { <entries sorted like the other interrupt controllers> } /Emil > cpu-map { > cluster0 { > core0 { > @@ -76,6 +92,10 @@ core0 { > core1 { > cpu = <&U74_1>; > }; > + > + core2 { > + cpu = <&E24>; > + }; > }; > }; > }; > -- > 2.37.0 >
On 11/07/2022 09:51, Emil Renner Berthing wrote: > On Sun, 10 Jul 2022 at 13:13, Conor Dooley <mail@conchuod.ie> wrote: >> >> From: Conor Dooley <conor.dooley@microchip.com> >> >> The JH7100 has a 32 bit monitor core that is missing from the device >> tree. Add it (and its cpu-map entry) to more accurately reflect the >> actual topology of the SoC. >> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >> --- >> arch/riscv/boot/dts/starfive/jh7100.dtsi | 20 ++++++++++++++++++++ >> 1 file changed, 20 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi >> index c617a61e26e2..840875fcb633 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi >> @@ -67,6 +67,22 @@ cpu1_intc: interrupt-controller { >> }; >> }; >> >> + E24: cpu@2 { >> + compatible = "sifive,e24", "riscv"; >> + device_type = "cpu"; >> + i-cache-block-size = <32>; >> + i-cache-sets = <256>; >> + i-cache-size = <16384>; >> + reg = <0x2>; >> + riscv,isa = "rv32imafc"; >> + status = "disabled"; >> + cpu2_intc: interrupt-controller { >> + #interrupt-cells = <1>; >> + compatible = "riscv,cpu-intc"; >> + interrupt-controller; >> + }; >> + }; > > Maybe you could make this look a bit more like the nodes above Sure. I'll send a proper patch to all the lists etc later with the order fixed. Thanks, Conor.
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index c617a61e26e2..840875fcb633 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -67,6 +67,22 @@ cpu1_intc: interrupt-controller { }; }; + E24: cpu@2 { + compatible = "sifive,e24", "riscv"; + device_type = "cpu"; + i-cache-block-size = <32>; + i-cache-sets = <256>; + i-cache-size = <16384>; + reg = <0x2>; + riscv,isa = "rv32imafc"; + status = "disabled"; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu-map { cluster0 { core0 { @@ -76,6 +92,10 @@ core0 { core1 { cpu = <&U74_1>; }; + + core2 { + cpu = <&E24>; + }; }; }; };