diff mbox series

[v1,1/2] dt-bindings: riscv: document the sifive e24

Message ID 20220711184325.1367393-2-mail@conchuod.ie (mailing list archive)
State New, archived
Headers show
Series Add the JH7100's Monitor Core | expand

Commit Message

Conor Dooley July 11, 2022, 6:43 p.m. UTC 
From: Conor Dooley <conor.dooley@microchip.com>

The SiFive E24 is a 32 bit monitor core present on the JH7100.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
 1 file changed, 2 insertions(+)

Comments

Krzysztof Kozlowski July 12, 2022, 8:08 a.m. UTC | #1 
On 11/07/2022 20:43, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> The SiFive E24 is a 32 bit monitor core present on the JH7100.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..195e762094a8 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -29,6 +29,7 @@  properties:
           - enum:
               - sifive,rocket0
               - sifive,bullet0
+              - sifive,e24
               - sifive,e5
               - sifive,e7
               - sifive,e71
@@ -75,6 +76,7 @@  properties:
       lowercase to simplify parsing.
     $ref: "/schemas/types.yaml#/definitions/string"
     enum:
+      - rv32imafc
       - rv64imac
       - rv64imafdc