| Message ID | 20220719054729.2224766-2-apatel@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Improve CLOCK_EVT_FEAT_C3STOP feature setting | expand |
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d632ac76532e..33832b8dfaab 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -78,6 +78,12 @@ properties: - rv64imac - rv64imafdc + riscv,timer-always-on: + type: boolean + description: + If present, the timer is powered through an always-on power + domain, therefore it never loses context. + # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false
We add an optional DT property riscv,timer-always-on which if present in CPU DT node then CPU timer is always powered-on and never loses context. Signed-off-by: Anup Patel <apatel@ventanamicro.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+)