| Message ID | 20220822112928.2727437-3-conor.dooley@microchip.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add PolarFire SoC Fabric Clock Conditioning Circuitry Support | expand |
On 22/08/2022 12:29, Conor Dooley wrote: > On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the > ordinal corners of the chip, which our documentation refers to as > "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are > highly configurable & many of the input clocks are optional. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > + clock-names: > + minItems: 2 > + items: > + - const: pll0_ref0 > + - const: pll0_ref1 > + - const: pll1_ref0 > + - const: pll1_ref1 > + - const: dll0_ref > + - const: dll1_ref > + > + '#clock-cells': > + const: 1 > + description: | > + The clock consumer should specify the desired clock by having the clock > + ID in its "clocks" phandle cell. > + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of > + PolarFire clock IDs. > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - clock-output-names Meh, didn't notice I had left this here.. Must've crept back in while I was rebasing my v2 changes. Either way Kryzysztof, I settled on removing the ordinal based naming entirely. I could not get trying the ordinal names & then falling back cleanly enough for my liking, so I dropped the whole thing. > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + clock-controller@38100000 { > + compatible = "microchip,mpfs-ccc"; > + reg = <0x38010000 0x1000>, <0x38020000 0x1000>, > + <0x39010000 0x1000>, <0x39020000 0x1000>; > + #clock-cells = <1>; > + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, > + <&refclk_ccc>, <&refclk_ccc>; > + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", > + "dll0_ref", "dll1_ref"; > + };
On Mon, 22 Aug 2022 12:29:25 +0100, Conor Dooley wrote: > On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the > ordinal corners of the chip, which our documentation refers to as > "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are > highly configurable & many of the input clocks are optional. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../bindings/clock/microchip,mpfs-ccc.yaml | 81 +++++++++++++++++++ > 1 file changed, 81 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.example.dtb: clock-controller@38100000: 'clock-output-names' is a required property From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On 22/08/2022 20:40, Rob Herring wrote: > On Mon, 22 Aug 2022 12:29:25 +0100, Conor Dooley wrote: >> On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the >> ordinal corners of the chip, which our documentation refers to as >> "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are >> highly configurable & many of the input clocks are optional. >> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >> --- >> .../bindings/clock/microchip,mpfs-ccc.yaml | 81 +++++++++++++++++++ >> 1 file changed, 81 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml >> > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): Heh, been waiting for this one all day. Messed up squashing commits before sending v2... fixed locally & I'll respin later in the week. I tried to mark it "changes required" in patchwork so you'd not waste time on it but I think that got reverted? Thanks, Conor. > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.example.dtb: clock-controller@38100000: 'clock-output-names' is a required property > From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/patch/ > > This check can fail if there are any dependencies. The base for a patch > series is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit. >
On Mon, Aug 22, 2022 at 07:44:20PM +0000, Conor.Dooley@microchip.com wrote: > On 22/08/2022 20:40, Rob Herring wrote: > > On Mon, 22 Aug 2022 12:29:25 +0100, Conor Dooley wrote: > >> On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the > >> ordinal corners of the chip, which our documentation refers to as > >> "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are > >> highly configurable & many of the input clocks are optional. > >> > >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > >> --- > >> .../bindings/clock/microchip,mpfs-ccc.yaml | 81 +++++++++++++++++++ > >> 1 file changed, 81 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml > >> > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > Heh, been waiting for this one all day. Messed up squashing commits > before sending v2... fixed locally & I'll respin later in the week. > I tried to mark it "changes required" in patchwork so you'd not waste > time on it but I think that got reverted? Could have. The CI job messes with the state and then I do, and my scripts don't expect the state changing underneath it. Most users don't have PW accounts. Don't worry, I don't spend much time on failing patches. Rob
diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml new file mode 100644 index 000000000000..eae291688f3e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry + +maintainers: + - Conor Dooley <conor.dooley@microchip.com> + +description: | + Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of + these blocks contains two PLLs and 2 DLLs & are located in the four corners of + the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at: + https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html + +properties: + compatible: + const: microchip,mpfs-ccc + + reg: + items: + - description: PLL0's control registers + - description: PLL1's control registers + - description: DLL0's control registers + - description: DLL1's control registers + + clocks: + description: + The CCC PLL's have two input clocks. It is required that even if the input + clocks are identical that both are provided. + minItems: 2 + items: + - description: PLL0's refclk0 + - description: PLL0's refclk1 + - description: PLL1's refclk0 + - description: PLL1's refclk1 + - description: DLL0's refclk + - description: DLL1's refclk + + clock-names: + minItems: 2 + items: + - const: pll0_ref0 + - const: pll0_ref1 + - const: pll1_ref0 + - const: pll1_ref1 + - const: dll0_ref + - const: dll1_ref + + '#clock-cells': + const: 1 + description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@38100000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x38010000 0x1000>, <0x38020000 0x1000>, + <0x39010000 0x1000>, <0x39020000 0x1000>; + #clock-cells = <1>; + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + };
On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the ordinal corners of the chip, which our documentation refers to as "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are highly configurable & many of the input clocks are optional. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- .../bindings/clock/microchip,mpfs-ccc.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml