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[3/4] RISC-V: preserve a1 in mcount

Message ID 20221027172435.2687118-4-jamie@jamieiles.com (mailing list archive)
State Superseded
Headers show
Series RISC-V: Dynamic ftrace support for RV32I | expand

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Commit Message

Jamie Iles Oct. 27, 2022, 5:24 p.m. UTC
The RISC-V ELF psABI states that both a0 and a1 are used for return
values so we should preserve them both in return_to_handler.  This is
especially important for RV32 for functions returning a 64-bit quantity
otherwise the return value can be corrupted and undefined behaviour
results.

Signed-off-by: Jamie Iles <jamie@jamieiles.com>
---
 arch/riscv/kernel/mcount.S | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Andrew Jones Oct. 28, 2022, 2:55 p.m. UTC | #1
On Thu, Oct 27, 2022 at 06:24:34PM +0100, Jamie Iles wrote:
> The RISC-V ELF psABI states that both a0 and a1 are used for return
> values so we should preserve them both in return_to_handler.  This is
> especially important for RV32 for functions returning a 64-bit quantity
> otherwise the return value can be corrupted and undefined behaviour
> results.
> 
> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
> ---
>  arch/riscv/kernel/mcount.S | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/kernel/mcount.S b/arch/riscv/kernel/mcount.S
> index 4166909ce7b3..5aa29509f047 100644
> --- a/arch/riscv/kernel/mcount.S
> +++ b/arch/riscv/kernel/mcount.S
> @@ -29,6 +29,7 @@
>  	REG_S	s0, 2*SZREG(sp)
>  	REG_S	ra, 3*SZREG(sp)
>  	REG_S	a0, 1*SZREG(sp)
> +	REG_S	a1, 0*SZREG(sp)
>  	addi	s0, sp, 32
>  	.endm
>  
> @@ -42,6 +43,7 @@
>  	REG_L	ra, 3*SZREG(sp)
>  	REG_L	s0, 2*SZREG(sp)
>  	REG_L	a0, 1*SZREG(sp)
> +	REG_L	a1, 0*SZREG(sp)
>  	addi	sp, sp, 4*SZREG
>  	.endm
>  
> @@ -71,9 +73,9 @@ ENTRY(return_to_handler)
>  	mv	a0, t6
>  #endif
>  	call	ftrace_return_to_handler
> -	mv	a1, a0
> +	mv	a2, a0
>  	RESTORE_RET_ABI_STATE
> -	jalr	a1
> +	jalr	a2
>  ENDPROC(return_to_handler)
>  #endif
>  
> -- 
> 2.34.1
>


Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff mbox series

Patch

diff --git a/arch/riscv/kernel/mcount.S b/arch/riscv/kernel/mcount.S
index 4166909ce7b3..5aa29509f047 100644
--- a/arch/riscv/kernel/mcount.S
+++ b/arch/riscv/kernel/mcount.S
@@ -29,6 +29,7 @@ 
 	REG_S	s0, 2*SZREG(sp)
 	REG_S	ra, 3*SZREG(sp)
 	REG_S	a0, 1*SZREG(sp)
+	REG_S	a1, 0*SZREG(sp)
 	addi	s0, sp, 32
 	.endm
 
@@ -42,6 +43,7 @@ 
 	REG_L	ra, 3*SZREG(sp)
 	REG_L	s0, 2*SZREG(sp)
 	REG_L	a0, 1*SZREG(sp)
+	REG_L	a1, 0*SZREG(sp)
 	addi	sp, sp, 4*SZREG
 	.endm
 
@@ -71,9 +73,9 @@  ENTRY(return_to_handler)
 	mv	a0, t6
 #endif
 	call	ftrace_return_to_handler
-	mv	a1, a0
+	mv	a2, a0
 	RESTORE_RET_ABI_STATE
-	jalr	a1
+	jalr	a2
 ENDPROC(return_to_handler)
 #endif