| Message ID | 20221121041757.418645-2-uwu@icenowy.me (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | Some DT binding quirks for T-Head C9xx | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/patch_count | success | Link |
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/build_warn_rv64 | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | WARNING: 'thead' may be misspelled - perhaps 'thread'? |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On 21/11/2022 05:17, Icenowy Zheng wrote: > T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not > compliant to the newcoming ACLINT spec) because of lack of mtime > register. > > Add a compatible string formatted like the C9xx-specific PLIC > compatible, and do not allow a SiFive one as fallback because they're > not really compliant. > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 11/20/22 22:17, Icenowy Zheng wrote: > T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not > compliant to the newcoming ACLINT spec) because of lack of mtime > register. > > Add a compatible string formatted like the C9xx-specific PLIC > compatible, and do not allow a SiFive one as fallback because they're > not really compliant. > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > --- > Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++++++ > 1 file changed, 8 insertions(+) Reviewed-by: Samuel Holland <samuel@sholland.org>
在 2022-11-21星期一的 12:17 +0800，Icenowy Zheng写道： > T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not > compliant to the newcoming ACLINT spec) because of lack of mtime > register. > > Add a compatible string formatted like the C9xx-specific PLIC > compatible, and do not allow a SiFive one as fallback because they're > not really compliant. > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Could this patch get applied individually? I want to drop the practice of the latter two patches and send new RFCs, and this patch is a dependency of some OpenSBI patch. > --- > Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 > ++++++++ > 1 file changed, 8 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index bbad24165837..aada6957216c 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -20,6 +20,10 @@ description: > property of "/cpus" DT node. The "timebase-frequency" DT property > is > described in Documentation/devicetree/bindings/riscv/cpus.yaml > > + T-Head C906/C910 CPU cores include an implementation of CLINT too, > however > + their implementation lacks a memory-mapped MTIME register, thus > not > + compatible with SiFive ones. > + > properties: > compatible: > oneOf: > @@ -29,6 +33,10 @@ properties: > - starfive,jh7100-clint > - canaan,k210-clint > - const: sifive,clint0 > + - items: > + - enum: > + - allwinner,sun20i-d1-clint > + - const: thead,c900-clint > - items: > - const: sifive,clint0 > - const: riscv,clint0
在 2022-11-21星期一的 12:17 +0800，Icenowy Zheng写道： > T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not > compliant to the newcoming ACLINT spec) because of lack of mtime > register. > > Add a compatible string formatted like the C9xx-specific PLIC > compatible, and do not allow a SiFive one as fallback because they're > not really compliant. > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Hi, could this patch be picked ASAP? Becuase it will be used then in further OpenSBI patches to enable proper operation of T-Head timer. I know the following 2 patches are in doubt and further rework for them are needed. > --- > Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 > ++++++++ > 1 file changed, 8 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index bbad24165837..aada6957216c 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -20,6 +20,10 @@ description: > property of "/cpus" DT node. The "timebase-frequency" DT property > is > described in Documentation/devicetree/bindings/riscv/cpus.yaml > > + T-Head C906/C910 CPU cores include an implementation of CLINT too, > however > + their implementation lacks a memory-mapped MTIME register, thus > not > + compatible with SiFive ones. > + > properties: > compatible: > oneOf: > @@ -29,6 +33,10 @@ properties: > - starfive,jh7100-clint > - canaan,k210-clint > - const: sifive,clint0 > + - items: > + - enum: > + - allwinner,sun20i-d1-clint > + - const: thead,c900-clint > - items: > - const: sifive,clint0 > - const: riscv,clint0
On Wed, Dec 07, 2022 at 06:47:26PM +0800, Icenowy Zheng wrote: > 在 2022-11-21星期一的 12:17 +0800，Icenowy Zheng写道： > > T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not > > compliant to the newcoming ACLINT spec) because of lack of mtime > > register. > > > > Add a compatible string formatted like the C9xx-specific PLIC > > compatible, and do not allow a SiFive one as fallback because they're > > not really compliant. > > > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > > Hi, could this patch be picked ASAP? Becuase it will be used then in > further OpenSBI patches to enable proper operation of T-Head timer. > > I know the following 2 patches are in doubt and further rework for them > are needed. Since it's me that's asking the questions about the other patches, but have no comments about this particular one: Acked-by: Conor Dooley <conor.dooley@microchip.com> HTH Icenowy! > > --- > > Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 > > ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > index bbad24165837..aada6957216c 100644 > > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > @@ -20,6 +20,10 @@ description: > > property of "/cpus" DT node. The "timebase-frequency" DT property > > is > > described in Documentation/devicetree/bindings/riscv/cpus.yaml > > > > + T-Head C906/C910 CPU cores include an implementation of CLINT too, > > however > > + their implementation lacks a memory-mapped MTIME register, thus > > not > > + compatible with SiFive ones. > > + > > properties: > > compatible: > > oneOf: > > @@ -29,6 +33,10 @@ properties: > > - starfive,jh7100-clint > > - canaan,k210-clint > > - const: sifive,clint0 > > + - items: > > + - enum: > > + - allwinner,sun20i-d1-clint > > + - const: thead,c900-clint > > - items: > > - const: sifive,clint0 > > - const: riscv,clint0 > >
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index bbad24165837..aada6957216c 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -20,6 +20,10 @@ description: property of "/cpus" DT node. The "timebase-frequency" DT property is described in Documentation/devicetree/bindings/riscv/cpus.yaml + T-Head C906/C910 CPU cores include an implementation of CLINT too, however + their implementation lacks a memory-mapped MTIME register, thus not + compatible with SiFive ones. + properties: compatible: oneOf: @@ -29,6 +33,10 @@ properties: - starfive,jh7100-clint - canaan,k210-clint - const: sifive,clint0 + - items: + - enum: + - allwinner,sun20i-d1-clint + - const: thead,c900-clint - items: - const: sifive,clint0 - const: riscv,clint0
T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not compliant to the newcoming ACLINT spec) because of lack of mtime register. Add a compatible string formatted like the C9xx-specific PLIC compatible, and do not allow a SiFive one as fallback because they're not really compliant. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++++++ 1 file changed, 8 insertions(+)