| Message ID | 20230103062610.69704-1-uwu@icenowy.me (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [RESEND,1/2] riscv: errata: fix T-Head dcache.cva encoding | expand |
在 2023-01-03星期二的 14:26 +0800，Icenowy Zheng写道： > The dcache.cva encoding shown in the comments are wrong, it's for > dcache.cval1 (which is restricted to L1) instead. > > Fix this in the comment and in the hardcoded instruction. > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com> Could this patch be included? As I know, at least two C910 SoCs will be generally available, T-Head's own TH1520 and Sophgo SG2042. > --- > Included when resending: > - Sergey's Tested-by tag. > > arch/riscv/include/asm/errata_list.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/errata_list.h > b/arch/riscv/include/asm/errata_list.h > index 4180312d2a70..605800bd390e 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -102,7 +102,7 @@ asm > volatile(ALTERNATIVE( \ > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > * 0000001 01001 rs1 000 00000 0001011 > * dcache.cva rs1 (clean, virtual address) > - * 0000001 00100 rs1 000 00000 0001011 > + * 0000001 00101 rs1 000 00000 0001011 > * > * dcache.cipa rs1 (clean then invalidate, physical address) > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > @@ -115,7 +115,7 @@ asm > volatile(ALTERNATIVE( \ > * 0000000 11001 00000 000 00000 0001011 > */ > #define THEAD_inval_A0 ".long 0x0265000b" > -#define THEAD_clean_A0 ".long 0x0245000b" > +#define THEAD_clean_A0 ".long 0x0255000b" > #define THEAD_flush_A0 ".long 0x0275000b" > #define THEAD_SYNC_S ".long 0x0190000b" >
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 4180312d2a70..605800bd390e 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE( \ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000001 01001 rs1 000 00000 0001011 * dcache.cva rs1 (clean, virtual address) - * 0000001 00100 rs1 000 00000 0001011 + * 0000001 00101 rs1 000 00000 0001011 * * dcache.cipa rs1 (clean then invalidate, physical address) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE( \ * 0000000 11001 00000 000 00000 0001011 */ #define THEAD_inval_A0 ".long 0x0265000b" -#define THEAD_clean_A0 ".long 0x0245000b" +#define THEAD_clean_A0 ".long 0x0255000b" #define THEAD_flush_A0 ".long 0x0275000b" #define THEAD_SYNC_S ".long 0x0190000b"