| Message ID | 20230106185526.260163-5-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | RISC-V non-coherent function pointer based cache management operations + non-coherent DMA support for AX45MP | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/patch_count | success | Link |
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 13 and now 13 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/alphanumeric_selects | success | Out of order selects before the patch: 57 and now 57 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/build_warn_rv64 | success | Errors and warnings before: 2054 this patch: 2054 |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | fail | Build failed |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | fail | Build failed |
On Fri, Jan 06, 2023 at 06:55:24PM +0000, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > describes the L2 cache block. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > v5 -> v6 > * Included RB tag from Geert I think not! > v4 -> v5 > * Dropped L2 cache configuration properties > * Dropped PMA configuration properties > * Ordered the required list to match the properties list > > RFC v3 -> v4 > * Dropped l2 cache configuration parameters > * s/larger/large > * Added minItems/maxItems for andestech,pma-regions > --- > .../cache/andestech,ax45mp-cache.yaml | 81 +++++++++++++++++++ > 1 file changed, 81 insertions(+) > create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > new file mode 100644 > index 000000000000..9f0be4835ad7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > @@ -0,0 +1,81 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright (C) 2022 Renesas Electronics Corp. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Andestech AX45MP L2 Cache Controller > + > +maintainers: > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > + > +description: > + A level-2 cache (L2C) is used to improve the system performance by providing > + a large amount of cache line entries and reasonable access delays. The L2C > + is shared between cores, and a non-inclusive non-exclusive policy is used. > + > +select: > + properties: > + compatible: > + contains: > + enum: > + - andestech,ax45mp-cache > + > + required: > + - compatible > + > +properties: > + compatible: > + items: > + - const: andestech,ax45mp-cache > + - const: cache You might find value in a specific compatible for your SoC & enforce constraints for it. Or you might not & I don't care either way :) Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor.
Hi Conor, Thank you for the review. On Fri, Jan 6, 2023 at 9:53 PM Conor Dooley <conor@kernel.org> wrote: > > On Fri, Jan 06, 2023 at 06:55:24PM +0000, Prabhakar wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > > describes the L2 cache block. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Rob Herring <robh@kernel.org> > > --- > > v5 -> v6 > > * Included RB tag from Geert > > I think not! > Sorry that was a typo. I meant Rob :) > > v4 -> v5 > > * Dropped L2 cache configuration properties > > * Dropped PMA configuration properties > > * Ordered the required list to match the properties list > > > > RFC v3 -> v4 > > * Dropped l2 cache configuration parameters > > * s/larger/large > > * Added minItems/maxItems for andestech,pma-regions > > --- > > .../cache/andestech,ax45mp-cache.yaml | 81 +++++++++++++++++++ > > 1 file changed, 81 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > > > diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > new file mode 100644 > > index 000000000000..9f0be4835ad7 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > @@ -0,0 +1,81 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +# Copyright (C) 2022 Renesas Electronics Corp. > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Andestech AX45MP L2 Cache Controller > > + > > +maintainers: > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > + > > +description: > > + A level-2 cache (L2C) is used to improve the system performance by providing > > + a large amount of cache line entries and reasonable access delays. The L2C > > + is shared between cores, and a non-inclusive non-exclusive policy is used. > > + > > +select: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - andestech,ax45mp-cache > > + > > + required: > > + - compatible > > + > > +properties: > > + compatible: > > + items: > > + - const: andestech,ax45mp-cache > > + - const: cache > > You might find value in a specific compatible for your SoC & enforce > constraints for it. Or you might not & I don't care either way :) > Good point actually. Geert what do you think? Cheers, Prabhakar
Hi Prabhakar, On Sat, Jan 7, 2023 at 9:47 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Fri, Jan 6, 2023 at 9:53 PM Conor Dooley <conor@kernel.org> wrote: > > On Fri, Jan 06, 2023 at 06:55:24PM +0000, Prabhakar wrote: > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > > > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > > > describes the L2 cache block. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > Reviewed-by: Rob Herring <robh@kernel.org> > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > > @@ -0,0 +1,81 @@ > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > +# Copyright (C) 2022 Renesas Electronics Corp. > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Andestech AX45MP L2 Cache Controller > > > + > > > +maintainers: > > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > + > > > +description: > > > + A level-2 cache (L2C) is used to improve the system performance by providing > > > + a large amount of cache line entries and reasonable access delays. The L2C > > > + is shared between cores, and a non-inclusive non-exclusive policy is used. > > > + > > > +select: > > > + properties: > > > + compatible: > > > + contains: > > > + enum: > > > + - andestech,ax45mp-cache > > > + > > > + required: > > > + - compatible > > > + > > > +properties: > > > + compatible: > > > + items: > > > + - const: andestech,ax45mp-cache > > > + - const: cache > > > > You might find value in a specific compatible for your SoC & enforce > > constraints for it. Or you might not & I don't care either way :) > > > Good point actually. Geert what do you think? That might be prudent, to cater for the way the standard AX45MP cache block is integrated into the RZ/Five (or any other) SoC. Still, in the absence of an SoC-specific compatible value, you can handle integration issues using soc_device_match(). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thanks for the feedback. On Mon, Jan 9, 2023 at 12:15 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Sat, Jan 7, 2023 at 9:47 PM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Fri, Jan 6, 2023 at 9:53 PM Conor Dooley <conor@kernel.org> wrote: > > > On Fri, Jan 06, 2023 at 06:55:24PM +0000, Prabhakar wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > > > > > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > > > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > > > > describes the L2 cache block. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Reviewed-by: Rob Herring <robh@kernel.org> > > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > > > @@ -0,0 +1,81 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > > +# Copyright (C) 2022 Renesas Electronics Corp. > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: Andestech AX45MP L2 Cache Controller > > > > + > > > > +maintainers: > > > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > + > > > > +description: > > > > + A level-2 cache (L2C) is used to improve the system performance by providing > > > > + a large amount of cache line entries and reasonable access delays. The L2C > > > > + is shared between cores, and a non-inclusive non-exclusive policy is used. > > > > + > > > > +select: > > > > + properties: > > > > + compatible: > > > > + contains: > > > > + enum: > > > > + - andestech,ax45mp-cache > > > > + > > > > + required: > > > > + - compatible > > > > + > > > > +properties: > > > > + compatible: > > > > + items: > > > > + - const: andestech,ax45mp-cache > > > > + - const: cache > > > > > > You might find value in a specific compatible for your SoC & enforce > > > constraints for it. Or you might not & I don't care either way :) > > > > > Good point actually. Geert what do you think? > > That might be prudent, to cater for the way the standard AX45MP cache > block is integrated into the RZ/Five (or any other) SoC. > > Still, in the absence of an SoC-specific compatible value, you can > handle integration issues using soc_device_match(). > Agreed, I'll continue with the current DT bindings. Cheers, Prabhakar
diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml new file mode 100644 index 000000000000..9f0be4835ad7 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2022 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andestech AX45MP L2 Cache Controller + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: + A level-2 cache (L2C) is used to improve the system performance by providing + a large amount of cache line entries and reasonable access delays. The L2C + is shared between cores, and a non-inclusive non-exclusive policy is used. + +select: + properties: + compatible: + contains: + enum: + - andestech,ax45mp-cache + + required: + - compatible + +properties: + compatible: + items: + - const: andestech,ax45mp-cache + - const: cache + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + cache-line-size: + const: 64 + + cache-level: + const: 2 + + cache-sets: + const: 1024 + + cache-size: + enum: [131072, 262144, 524288, 1048576, 2097152] + + cache-unified: true + + next-level-cache: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - cache-line-size + - cache-level + - cache-sets + - cache-size + - cache-unified + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + cache-controller@2010000 { + compatible = "andestech,ax45mp-cache", "cache"; + reg = <0x13400000 0x100000>; + interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <262144>; + cache-unified; + };