| Message ID | 20230130120128.1349464-3-ajones@ventanamicro.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | RISC-V: Apply Zicboz to clear_page | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes or riscv/for-next |
Hey! On Mon, Jan 30, 2023 at 01:01:24PM +0100, Andrew Jones wrote: > The Zicboz operation (cbo.zero) operates on a block-size defined > for the cpu-core. While we already have the riscv,cbom-block-size > property, it only provides the block size for Zicbom operations. > Even though it's likely Zicboz and Zicbom will use the same size, > that's not specified. If you end up respinning for some other reason, perhaps: s/that's not specified/that's not required by the specification/ or some other wording to that effect? I'm assuming by "specified" you're referring to the cmobase spec, but that wording I don't think is particular clear. > Create another property specifically for > Zicboz. > > Cc: Rob Herring <robh@kernel.org> > Signed-off-by: Andrew Jones <ajones@ventanamicro.com> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index c6720764e765..f4ee70f8e1cf 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -72,6 +72,11 @@ properties: > description: > The blocksize in bytes for the Zicbom cache operations. > > + riscv,cboz-block-size: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + The blocksize in bytes for the Zicboz cache operations. > + I was happy with either keeping them apart entirely or a having this one default to the value of cbom-block-size, so: Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor.
On Mon, 30 Jan 2023 13:01:24 +0100, Andrew Jones wrote: > The Zicboz operation (cbo.zero) operates on a block-size defined > for the cpu-core. While we already have the riscv,cbom-block-size > property, it only provides the block size for Zicbom operations. > Even though it's likely Zicboz and Zicbom will use the same size, > that's not specified. Create another property specifically for > Zicboz. > > Cc: Rob Herring <robh@kernel.org> > Signed-off-by: Andrew Jones <ajones@ventanamicro.com> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6720764e765..f4ee70f8e1cf 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -72,6 +72,11 @@ properties: description: The blocksize in bytes for the Zicbom cache operations. + riscv,cboz-block-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The blocksize in bytes for the Zicboz cache operations. + riscv,isa: description: Identifies the specific RISC-V instruction set architecture
The Zicboz operation (cbo.zero) operates on a block-size defined for the cpu-core. While we already have the riscv,cbom-block-size property, it only provides the block size for Zicbom operations. Even though it's likely Zicboz and Zicbom will use the same size, that's not specified. Create another property specifically for Zicboz. Cc: Rob Herring <robh@kernel.org> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ 1 file changed, 5 insertions(+)