| Message ID | 20230307211053.1777066-1-conor@kernel.org (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | riscv: dts: microchip: fix the mpfs' mailbox regs | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Single patches do not need cover letters |
| conchuod/tree_selection | success | Guessed tree name to be for-next |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 1 and now 1 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 21 this patch: 21 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 37 this patch: 37 |
| conchuod/alphanumeric_selects | success | Out of order selects before the patch: 728 and now 728 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 9 lines checked |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Tue, 07 Mar 2023 13:10:54 PST (-0800), Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The mailbox on PolarFire SoC should really have three reg properties, > not two. Without splitting into three sections, the system controller's > QSPI cannot be accessed as it sits inside the current first range. The > driver & binding have been adapted to account for both two & three > ranges, so fix the dts too. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/boot/dts/microchip/mpfs.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi > index 0a9bb84af438..62b1aec4ffff 100644 > --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi > +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi > @@ -498,7 +498,8 @@ usb: usb@20201000 { > > mbox: mailbox@37020000 { > compatible = "microchip,mpfs-mailbox"; > - reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; > + reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, > + <0x0 0x37020800 0x0 0x100>; > interrupt-parent = <&plic>; > interrupts = <96>; > #mbox-cells = <1>; Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
From: Conor Dooley <conor.dooley@microchip.com> On Tue, 07 Mar 2023 21:10:54 +0000, Conor Dooley wrote: > The mailbox on PolarFire SoC should really have three reg properties, > not two. Without splitting into three sections, the system controller's > QSPI cannot be accessed as it sits inside the current first range. The > driver & binding have been adapted to account for both two & three > ranges, so fix the dts too. > > > [...] Applied to riscv-dt-for-next, thanks! [1/1] riscv: dts: microchip: fix the mpfs' mailbox regs https://git.kernel.org/conor/c/e77da13b8e36 Thanks, Conor.
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 0a9bb84af438..62b1aec4ffff 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -498,7 +498,8 @@ usb: usb@20201000 { mbox: mailbox@37020000 { compatible = "microchip,mpfs-mailbox"; - reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, + <0x0 0x37020800 0x0 0x100>; interrupt-parent = <&plic>; interrupts = <96>; #mbox-cells = <1>;