[-next,v16,01/20] riscv: Rename __switch_to_aux() -> fpu

Message ID	20230323145924.4194-2-andy.chiu@sifive.com (mailing list archive)
State	Superseded
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Guo Ren <ren_guo@c-sky.com>, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>, Conor Dooley <conor.dooley@microchip.com>, Heiko Stuebner <heiko.stuebner@vrull.eu>, Jisheng Zhang <jszhang@kernel.org> Subject: [PATCH -next v16 01/20] riscv: Rename __switch_to_aux() -> fpu Date: Thu, 23 Mar 2023 14:59:05 +0000 Message-Id: <20230323145924.4194-2-andy.chiu@sifive.com> In-Reply-To: <20230323145924.4194-1-andy.chiu@sifive.com> References: <20230323145924.4194-1-andy.chiu@sifive.com> Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	riscv: Add vector ISA support \| expand [-next,v16,00/20] riscv: Add vector ISA support [-next,v16,01/20] riscv: Rename __switch_to_aux() -> fpu [-next,v16,02/20] riscv: Extending cpufeature.c to detect V-extension [-next,v16,03/20] riscv: Add new csr defines related to vector extension [-next,v16,04/20] riscv: Clear vector regfile on bootup [-next,v16,05/20] riscv: Disable Vector Instructions for kernel itself [-next,v16,06/20] riscv: Introduce Vector enable/disable helpers [-next,v16,07/20] riscv: Introduce riscv_v_vsize to record size of Vector context [-next,v16,08/20] riscv: Introduce struct/helpers to save/restore per-task Vector state [-next,v16,09/20] riscv: Add task switch support for vector [-next,v16,10/20] riscv: Allocate user's vector context in the first-use trap [-next,v16,11/20] riscv: Add ptrace vector support [-next,v16,12/20] riscv: signal: check fp-reserved words unconditionally [-next,v16,13/20] riscv: signal: Add sigcontext save/restore for vector [-next,v16,14/20] riscv: signal: Report signal frame size to userspace via auxv [-next,v16,15/20] riscv: signal: validate altstack to reflect Vector [-next,v16,16/20] riscv: prevent stack corruption by reserving task_pt_regs(p) early [-next,v16,17/20] riscv: kvm: Add V extension to KVM ISA [-next,v16,18/20] riscv: KVM: Add vector lazy save/restore support [-next,v16,19/20] riscv: detect assembler support for .option arch [-next,v16,20/20] riscv: Enable Vector code to be built

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20230323145924.4194-2-andy.chiu@sifive.com (mailing list archive)

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Superseded

Headers

From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org,
	palmer@dabbelt.com,
	anup@brainfault.org,
	atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org,
	kvm@vger.kernel.org
Cc: vineetg@rivosinc.com,
	greentime.hu@sifive.com,
	guoren@linux.alibaba.com,
	Guo Ren <ren_guo@c-sky.com>,
	Andy Chiu <andy.chiu@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Guo Ren <guoren@kernel.org>,
	Conor Dooley <conor.dooley@microchip.com>,
	Heiko Stuebner <heiko.stuebner@vrull.eu>,
	Jisheng Zhang <jszhang@kernel.org>
Subject: [PATCH -next v16 01/20] riscv: Rename __switch_to_aux() -> fpu
Date: Thu, 23 Mar 2023 14:59:05 +0000
Message-Id: <20230323145924.4194-2-andy.chiu@sifive.com>
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Series

riscv: Add vector ISA support | expand

Context	Check	Description
conchuod/apply	fail	Patch does not apply to for-next
conchuod/tree_selection	fail	Failed to apply to next/pending-fixes or riscv/for-next

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Commit Message

Andy Chiu March 23, 2023, 2:59 p.m. UTC

From: Guo Ren <ren_guo@c-sky.com>

The name of __switch_to_aux() is not clear and rename it with the
determine function: __switch_to_fpu(). Next we could add other regs'
switch.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/include/asm/switch_to.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 60f8ca01d36e..4b96b13dee27 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -46,7 +46,7 @@  static inline void fstate_restore(struct task_struct *task,
 	}
 }
 
-static inline void __switch_to_aux(struct task_struct *prev,
+static inline void __switch_to_fpu(struct task_struct *prev,
 				   struct task_struct *next)
 {
 	struct pt_regs *regs;
@@ -66,7 +66,7 @@  static __always_inline bool has_fpu(void)
 static __always_inline bool has_fpu(void) { return false; }
 #define fstate_save(task, regs) do { } while (0)
 #define fstate_restore(task, regs) do { } while (0)
-#define __switch_to_aux(__prev, __next) do { } while (0)
+#define __switch_to_fpu(__prev, __next) do { } while (0)
 #endif
 
 extern struct task_struct *__switch_to(struct task_struct *,
@@ -77,7 +77,7 @@  do {							\
 	struct task_struct *__prev = (prev);		\
 	struct task_struct *__next = (next);		\
 	if (has_fpu())					\
-		__switch_to_aux(__prev, __next);	\
+		__switch_to_fpu(__prev, __next);	\
 	((last) = __switch_to(__prev, __next));		\
 } while (0)

[-next,v16,01/20] riscv: Rename __switch_to_aux() -> fpu

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