| Message ID | 20230428120120.21620-1-alexghiti@rivosinc.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [-fixes,1/2] riscv: Fix huge_ptep_set_wrprotect when PTE is a NAPOT | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Single patches do not need cover letters |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD 3ec1aafb0ff9 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 1 and now 1 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 18 this patch: 18 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 18 this patch: 18 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | WARNING: Unknown commit id 'f2aeb0118ddd', maybe rebased or not pulled? |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | fail | Problems with Fixes tag: 1 |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Fri, Apr 28, 2023 at 02:01:19PM +0200, Alexandre Ghiti wrote: > We need to avoid inconsistencies across the PTEs that form a NAPOT > region, so when we write protect such a region, we should clear and flush > all the PTEs to make sure that any of those PTEs is not cached which would > result in such inconsistencies (arm64 does the same). > > Fixes: f2aeb0118ddd ("riscv: mm: support Svnapot in hugetlb page") > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> > --- > arch/riscv/mm/hugetlbpage.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/mm/hugetlbpage.c b/arch/riscv/mm/hugetlbpage.c > index a163a3e0f0d4..238d00bdac14 100644 > --- a/arch/riscv/mm/hugetlbpage.c > +++ b/arch/riscv/mm/hugetlbpage.c > @@ -218,6 +218,7 @@ void huge_ptep_set_wrprotect(struct mm_struct *mm, > { > pte_t pte = ptep_get(ptep); > unsigned long order; > + pte_t orig_pte; > int i, pte_num; > > if (!pte_napot(pte)) { > @@ -228,9 +229,12 @@ void huge_ptep_set_wrprotect(struct mm_struct *mm, > order = napot_cont_order(pte); > pte_num = napot_pte_num(order); > ptep = huge_pte_offset(mm, addr, napot_cont_size(order)); > + orig_pte = get_clear_contig_flush(mm, addr, ptep, pte_num); > + > + orig_pte = pte_wrprotect(orig_pte); > > for (i = 0; i < pte_num; i++, addr += PAGE_SIZE, ptep++) > - ptep_set_wrprotect(mm, addr, ptep); > + set_pte_at(mm, addr, ptep, orig_pte); > } > > pte_t huge_ptep_clear_flush(struct vm_area_struct *vma, > -- > 2.37.2 > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
On Fri, Apr 28, 2023 at 02:01:19PM +0200, Alexandre Ghiti wrote: > We need to avoid inconsistencies across the PTEs that form a NAPOT > region, so when we write protect such a region, we should clear and flush > all the PTEs to make sure that any of those PTEs is not cached which would > result in such inconsistencies (arm64 does the same). > > Fixes: f2aeb0118ddd ("riscv: mm: support Svnapot in hugetlb page") For both patches I get: Commit: 0146c955ff59 ("riscv: Fix huge_ptep_set_wrprotect when PTE is a NAPOT") Fixes tag: Fixes: f2aeb0118ddd ("riscv: mm: support Svnapot in hugetlb page") Has these problem(s): - Target SHA1 does not exist This particular one is 82a1a1f3bfb6 in riscv/for-next. Cheers, Conor.
On Fri, 28 Apr 2023 14:01:19 +0200, Alexandre Ghiti wrote: > We need to avoid inconsistencies across the PTEs that form a NAPOT > region, so when we write protect such a region, we should clear and flush > all the PTEs to make sure that any of those PTEs is not cached which would > result in such inconsistencies (arm64 does the same). > > Applied, thanks! [1/2] riscv: Fix huge_ptep_set_wrprotect when PTE is a NAPOT https://git.kernel.org/palmer/c/d22ce4f4137a [2/2] riscv: Implement missing huge_ptep_get https://git.kernel.org/palmer/c/640ad2677d56 Best regards,
diff --git a/arch/riscv/mm/hugetlbpage.c b/arch/riscv/mm/hugetlbpage.c index a163a3e0f0d4..238d00bdac14 100644 --- a/arch/riscv/mm/hugetlbpage.c +++ b/arch/riscv/mm/hugetlbpage.c @@ -218,6 +218,7 @@ void huge_ptep_set_wrprotect(struct mm_struct *mm, { pte_t pte = ptep_get(ptep); unsigned long order; + pte_t orig_pte; int i, pte_num; if (!pte_napot(pte)) { @@ -228,9 +229,12 @@ void huge_ptep_set_wrprotect(struct mm_struct *mm, order = napot_cont_order(pte); pte_num = napot_pte_num(order); ptep = huge_pte_offset(mm, addr, napot_cont_size(order)); + orig_pte = get_clear_contig_flush(mm, addr, ptep, pte_num); + + orig_pte = pte_wrprotect(orig_pte); for (i = 0; i < pte_num; i++, addr += PAGE_SIZE, ptep++) - ptep_set_wrprotect(mm, addr, ptep); + set_pte_at(mm, addr, ptep, orig_pte); } pte_t huge_ptep_clear_flush(struct vm_area_struct *vma,
We need to avoid inconsistencies across the PTEs that form a NAPOT region, so when we write protect such a region, we should clear and flush all the PTEs to make sure that any of those PTEs is not cached which would result in such inconsistencies (arm64 does the same). Fixes: f2aeb0118ddd ("riscv: mm: support Svnapot in hugetlb page") Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> --- arch/riscv/mm/hugetlbpage.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)