| Message ID | 20230508-decibel-fender-532248c8f8ed@spud (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | Deprecate riscv,isa DT property? | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes or riscv/for-next |
On 08/05/2023 20:16, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > C'est la vie, the spec folks reserve the ability to make incompatible > changes between major versions of an extension. Their idea of backwards > compatibility appears driven by the hardware perspective - it's > backwards compatible if a later version is a subset of the existing > extension. IOW, if you supported `x` in vN, you still support `x` in > vN+1. > However in software terms, code that was built for the vN's `x` > extension may not work with the new definition. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index db5253a2a74a..405915b04d69 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -91,6 +91,9 @@ properties: Notably, riscv,isa was defined prior to the creation of the Zicsr and Zifencei extensions and thus "i" implies "zicsr_zifencei". + For the sake of backwards compatibility, an unversioned + extension means that the hart/platform is capable of + supporting version 1.0.0 of the extension. While the isa strings in ISA specification are case insensitive, letters in the riscv,isa string must be all