diff mbox series

[RFC,6/6] riscv: dts: microchip: use new riscv,isa-extension-* properties for mpfs

Message ID 20230508-elf-dismay-799bb48a635e@spud (mailing list archive)
State Changes Requested
Delegated to: Conor Dooley
Headers show
Series Deprecate riscv,isa DT property? | expand

Checks

Context Check Description
conchuod/tree_selection fail Failed to apply to next/pending-fixes or riscv/for-next

Commit Message

Conor Dooley May 8, 2023, 6:16 p.m. UTC 
From: Conor Dooley <conor.dooley@microchip.com>

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/mpfs.dtsi | 42 ++++++++++++++++++++++---
 1 file changed, 37 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 104504352e99..53efb5e03c64 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -21,7 +21,11 @@  cpu0: cpu@0 {
 			i-cache-sets = <128>;
 			i-cache-size = <16384>;
 			reg = <0>;
-			riscv,isa = "rv64imac";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			status = "disabled";
 
@@ -47,7 +51,14 @@  cpu1: cpu@1 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			reg = <1>;
-			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-f = "v1.0.0";
+			riscv,isa-extension-d = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
+			riscv,isa-extension-zicsr = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;
@@ -75,7 +86,14 @@  cpu2: cpu@2 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			reg = <2>;
-			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-f = "v1.0.0";
+			riscv,isa-extension-d = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
+			riscv,isa-extension-zicsr = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;
@@ -103,7 +121,14 @@  cpu3: cpu@3 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			reg = <3>;
-			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-f = "v1.0.0";
+			riscv,isa-extension-d = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
+			riscv,isa-extension-zicsr = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;
@@ -131,7 +156,14 @@  cpu4: cpu@4 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			reg = <4>;
-			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-f = "v1.0.0";
+			riscv,isa-extension-d = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
+			riscv,isa-extension-zicsr = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;