| Message ID | 20230512085321.13259-7-alexghiti@rivosinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: Allow userspace to directly access perf counters | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes or riscv/for-next |
On Fri, May 12, 2023 at 10:53:17AM +0200, Alexandre Ghiti wrote: > Implement the needed callbacks in the legacy driver so that we can > directly access the counters through perf in userspace. > > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> > --- > drivers/perf/riscv_pmu_legacy.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c > index ffe09d857366..f0f5bd856f66 100644 > --- a/drivers/perf/riscv_pmu_legacy.c > +++ b/drivers/perf/riscv_pmu_legacy.c > @@ -74,6 +74,31 @@ static void pmu_legacy_ctr_start(struct perf_event *event, u64 ival) > local64_set(&hwc->prev_count, initial_val); > } > > +static uint8_t pmu_legacy_csr_index(struct perf_event *event) > +{ > + return event->hw.idx; > +} > + > +static void pmu_legacy_event_mapped(struct perf_event *event, struct mm_struct *mm) > +{ > + /* In legacy mode, the first 3 CSRs are available. */ Shouldn't this be /* In legacy mode, the first and third CSR are available. */ ? > + if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES && > + event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) > + return; > + > + event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT; > +} > + > +static void pmu_legacy_event_unmapped(struct perf_event *event, struct mm_struct *mm) > +{ > + /* In legacy mode, the first 3 CSRs are available. */ same comment > + if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES && > + event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) > + return; > + > + event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT; > +} > + > /* > * This is just a simple implementation to allow legacy implementations > * compatible with new RISC-V PMU driver framework. > @@ -94,6 +119,9 @@ static void pmu_legacy_init(struct riscv_pmu *pmu) > pmu->ctr_get_width = NULL; > pmu->ctr_clear_idx = NULL; > pmu->ctr_read = pmu_legacy_read_ctr; > + pmu->event_mapped = pmu_legacy_event_mapped; > + pmu->event_unmapped = pmu_legacy_event_unmapped; > + pmu->csr_index = pmu_legacy_csr_index; > > perf_pmu_register(&pmu->pmu, RISCV_PMU_LEGACY_PDEV_NAME, PERF_TYPE_RAW); > } > -- > 2.37.2 > Otherwise, Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
On 31/05/2023 16:27, Andrew Jones wrote: > On Fri, May 12, 2023 at 10:53:17AM +0200, Alexandre Ghiti wrote: >> Implement the needed callbacks in the legacy driver so that we can >> directly access the counters through perf in userspace. >> >> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> >> --- >> drivers/perf/riscv_pmu_legacy.c | 28 ++++++++++++++++++++++++++++ >> 1 file changed, 28 insertions(+) >> >> diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c >> index ffe09d857366..f0f5bd856f66 100644 >> --- a/drivers/perf/riscv_pmu_legacy.c >> +++ b/drivers/perf/riscv_pmu_legacy.c >> @@ -74,6 +74,31 @@ static void pmu_legacy_ctr_start(struct perf_event *event, u64 ival) >> local64_set(&hwc->prev_count, initial_val); >> } >> >> +static uint8_t pmu_legacy_csr_index(struct perf_event *event) >> +{ >> + return event->hw.idx; >> +} >> + >> +static void pmu_legacy_event_mapped(struct perf_event *event, struct mm_struct *mm) >> +{ >> + /* In legacy mode, the first 3 CSRs are available. */ > Shouldn't this be > > /* In legacy mode, the first and third CSR are available. */ > > ? Yes, I guess this comment is not right in this context, so I'll remove the comment entirely as it does bring much. >> + if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES && >> + event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) >> + return; >> + >> + event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT; >> +} >> + >> +static void pmu_legacy_event_unmapped(struct perf_event *event, struct mm_struct *mm) >> +{ >> + /* In legacy mode, the first 3 CSRs are available. */ > same comment > >> + if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES && >> + event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) >> + return; >> + >> + event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT; >> +} >> + >> /* >> * This is just a simple implementation to allow legacy implementations >> * compatible with new RISC-V PMU driver framework. >> @@ -94,6 +119,9 @@ static void pmu_legacy_init(struct riscv_pmu *pmu) >> pmu->ctr_get_width = NULL; >> pmu->ctr_clear_idx = NULL; >> pmu->ctr_read = pmu_legacy_read_ctr; >> + pmu->event_mapped = pmu_legacy_event_mapped; >> + pmu->event_unmapped = pmu_legacy_event_unmapped; >> + pmu->csr_index = pmu_legacy_csr_index; >> >> perf_pmu_register(&pmu->pmu, RISCV_PMU_LEGACY_PDEV_NAME, PERF_TYPE_RAW); >> } >> -- >> 2.37.2 >> > Otherwise, > > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Thanks!
diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c index ffe09d857366..f0f5bd856f66 100644 --- a/drivers/perf/riscv_pmu_legacy.c +++ b/drivers/perf/riscv_pmu_legacy.c @@ -74,6 +74,31 @@ static void pmu_legacy_ctr_start(struct perf_event *event, u64 ival) local64_set(&hwc->prev_count, initial_val); } +static uint8_t pmu_legacy_csr_index(struct perf_event *event) +{ + return event->hw.idx; +} + +static void pmu_legacy_event_mapped(struct perf_event *event, struct mm_struct *mm) +{ + /* In legacy mode, the first 3 CSRs are available. */ + if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES && + event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) + return; + + event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT; +} + +static void pmu_legacy_event_unmapped(struct perf_event *event, struct mm_struct *mm) +{ + /* In legacy mode, the first 3 CSRs are available. */ + if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES && + event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) + return; + + event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT; +} + /* * This is just a simple implementation to allow legacy implementations * compatible with new RISC-V PMU driver framework. @@ -94,6 +119,9 @@ static void pmu_legacy_init(struct riscv_pmu *pmu) pmu->ctr_get_width = NULL; pmu->ctr_clear_idx = NULL; pmu->ctr_read = pmu_legacy_read_ctr; + pmu->event_mapped = pmu_legacy_event_mapped; + pmu->event_unmapped = pmu_legacy_event_unmapped; + pmu->csr_index = pmu_legacy_csr_index; perf_pmu_register(&pmu->pmu, RISCV_PMU_LEGACY_PDEV_NAME, PERF_TYPE_RAW); }
Implement the needed callbacks in the legacy driver so that we can directly access the counters through perf in userspace. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> --- drivers/perf/riscv_pmu_legacy.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)