diff mbox series

[2/5] Documentation: riscv: vector: Wrap control_argument struct definition in code block

Message ID 20230514090432.78217-3-bagasdotme@gmail.com (mailing list archive)
State Handled Elsewhere
Headers show
Series riscv: Fixes for vector extension documentation | expand

Checks

Context Check Description
conchuod/tree_selection fail Failed to apply to next/pending-fixes or riscv/for-next

Commit Message

Bagas Sanjaya May 14, 2023, 9:04 a.m. UTC
kernel test robot reports htmldocs warning:

Documentation/riscv/vector.rst:45: WARNING: Definition list ends without a blank line; unexpected unindent.

The warning is due to definition of control_argument struct, written
unformatted. Wrap it in code block with C syntax highlighting to fix the
warning.

Fixes: 412c68cfeeb178 ("riscv: Add documentation for Vector")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202305141409.bEBvlSY4-lkp@intel.com/
Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com>
---
 Documentation/riscv/vector.rst | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)
diff mbox series

Patch

diff --git a/Documentation/riscv/vector.rst b/Documentation/riscv/vector.rst
index acc97508ccb249..178b3f3f452462 100644
--- a/Documentation/riscv/vector.rst
+++ b/Documentation/riscv/vector.rst
@@ -36,14 +36,16 @@  prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg)
     be interpreted as the following structure, and accessed by 3 masks
     respectively.
 
-    struct control_argument {
-        // Located by PR_RISCV_V_VSTATE_CTRL_CUR_MASK
-        int current_enablement_status : 2;
-        // Located by PR_RISCV_V_VSTATE_CTRL_NEXT_MASK
-        int next_enablement_status : 2;
-        // Located by PR_RISCV_V_VSTATE_CTRL_INHERIT
-        bool inherit_mode : 1;
-    }
+    .. code-block:: c
+
+        struct control_argument {
+            // Located by PR_RISCV_V_VSTATE_CTRL_CUR_MASK
+            int current_enablement_status : 2;
+            // Located by PR_RISCV_V_VSTATE_CTRL_NEXT_MASK
+            int next_enablement_status : 2;
+            // Located by PR_RISCV_V_VSTATE_CTRL_INHERIT
+            bool inherit_mode : 1;
+        }
 
     The 3 masks, PR_RISCV_V_VSTATE_CTRL_CUR_MASK,
     PR_RISCV_V_VSTATE_CTRL_NEXT_MASK, and PR_RISCV_V_VSTATE_CTRL_INHERIT