diff mbox series

[3/5] Documentation: riscv: vector: Use bullet lists for prctl list

Message ID 20230514090432.78217-4-bagasdotme@gmail.com (mailing list archive)
State Handled Elsewhere
Headers show
Series riscv: Fixes for vector extension documentation | expand

Checks

Context Check Description
conchuod/tree_selection fail Failed to apply to next/pending-fixes or riscv/for-next

Commit Message

Bagas Sanjaya May 14, 2023, 9:04 a.m. UTC
The documentation lists two userspace prctl() calls. Use bullet
lists for the listing.

Fixes: 412c68cfeeb178 ("riscv: Add documentation for Vector")
Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com>
---
 Documentation/riscv/vector.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Conor Dooley May 14, 2023, 9:49 a.m. UTC | #1
Hey Bagas,

On Sun, May 14, 2023 at 04:04:30PM +0700, Bagas Sanjaya wrote:
> The documentation lists two userspace prctl() calls. Use bullet
> lists for the listing.
> 
> Fixes: 412c68cfeeb178 ("riscv: Add documentation for Vector")

Firstly, these fixes commit hashes would not be stable as this series
has been applied to riscv/for-next [1]. But also, from this commit
onwards, things seem like stylistic comments that would be undeserving
of a Fixes: tag to begin with.
Perhaps you'd be better off suggesting these changes in response to the
original thread [2], so that it goes in "correctly" in the first place?
Andy has to re-submit anyway as there are a few bugs that crept in in
the most recent revision of his series.

Thanks,
Conor.

1 - https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/log/?h=for-next
2 - https://lore.kernel.org/linux-riscv/20230509103033.11285-25-andy.chiu@sifive.com/

> Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com>
> ---
>  Documentation/riscv/vector.rst | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/riscv/vector.rst b/Documentation/riscv/vector.rst
> index 178b3f3f452462..c7bd701c7963b6 100644
> --- a/Documentation/riscv/vector.rst
> +++ b/Documentation/riscv/vector.rst
> @@ -13,7 +13,7 @@ order to support the use of the RISC-V Vector Extension.
>  Two new prctl() calls are added to allow programs to manage the enablement
>  status for the use of Vector in userspace:
>  
> -prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg)
> +* prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg)
>  
>      Sets the Vector enablement status of the calling thread, where the control
>      argument consists of two 2-bit enablement statuses and a bit for inheritance
> @@ -89,7 +89,7 @@ prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg)
>          * Every successful call overwrites a previous setting for the calling
>            thread.
>  
> -prctl(PR_RISCV_V_SET_CONTROL)
> +* prctl(PR_RISCV_V_SET_CONTROL)
>  
>      Gets the same Vector enablement status for the calling thread. Setting for
>      next execve() call and the inheritance bit are all OR-ed together.
> -- 
> An old man doll... just what I always wanted! - Clara
>
Andy Chiu May 16, 2023, 2:28 p.m. UTC | #2
Hi Bagas,

On Sun, May 14, 2023 at 5:49 PM Conor Dooley <conor@kernel.org> wrote:
>
> Hey Bagas,
>
> On Sun, May 14, 2023 at 04:04:30PM +0700, Bagas Sanjaya wrote:
> > The documentation lists two userspace prctl() calls. Use bullet
> > lists for the listing.
> >
> > Fixes: 412c68cfeeb178 ("riscv: Add documentation for Vector")
>
> Firstly, these fixes commit hashes would not be stable as this series
> has been applied to riscv/for-next [1]. But also, from this commit
> onwards, things seem like stylistic comments that would be undeserving
> of a Fixes: tag to begin with.
> Perhaps you'd be better off suggesting these changes in response to the
> original thread [2], so that it goes in "correctly" in the first place?
> Andy has to re-submit anyway as there are a few bugs that crept in in
> the most recent revision of his series.
>
> Thanks,
> Conor.
>
> 1 - https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/log/?h=for-next
> 2 - https://lore.kernel.org/linux-riscv/20230509103033.11285-25-andy.chiu@sifive.com/
>
> > Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com>
> > ---
> >  Documentation/riscv/vector.rst | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/riscv/vector.rst b/Documentation/riscv/vector.rst
> > index 178b3f3f452462..c7bd701c7963b6 100644
> > --- a/Documentation/riscv/vector.rst
> > +++ b/Documentation/riscv/vector.rst
> > @@ -13,7 +13,7 @@ order to support the use of the RISC-V Vector Extension.
> >  Two new prctl() calls are added to allow programs to manage the enablement
> >  status for the use of Vector in userspace:
> >
> > -prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg)
> > +* prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg)
> >
> >      Sets the Vector enablement status of the calling thread, where the control
> >      argument consists of two 2-bit enablement statuses and a bit for inheritance
> > @@ -89,7 +89,7 @@ prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg)
> >          * Every successful call overwrites a previous setting for the calling
> >            thread.
> >
> > -prctl(PR_RISCV_V_SET_CONTROL)
> > +* prctl(PR_RISCV_V_SET_CONTROL)
> >
> >      Gets the same Vector enablement status for the calling thread. Setting for
> >      next execve() call and the inheritance bit are all OR-ed together.
> > --
> > An old man doll... just what I always wanted! - Clara
> >

Thanks for fixing the document. Do you mind if I merge them into my
patch and add you as a co-developer? I think merging those fixes into
the one original patch would be much cleaner than providing fix
patches afterward.

Thanks,
Andy
diff mbox series

Patch

diff --git a/Documentation/riscv/vector.rst b/Documentation/riscv/vector.rst
index 178b3f3f452462..c7bd701c7963b6 100644
--- a/Documentation/riscv/vector.rst
+++ b/Documentation/riscv/vector.rst
@@ -13,7 +13,7 @@  order to support the use of the RISC-V Vector Extension.
 Two new prctl() calls are added to allow programs to manage the enablement
 status for the use of Vector in userspace:
 
-prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg)
+* prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg)
 
     Sets the Vector enablement status of the calling thread, where the control
     argument consists of two 2-bit enablement statuses and a bit for inheritance
@@ -89,7 +89,7 @@  prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg)
         * Every successful call overwrites a previous setting for the calling
           thread.
 
-prctl(PR_RISCV_V_SET_CONTROL)
+* prctl(PR_RISCV_V_SET_CONTROL)
 
     Gets the same Vector enablement status for the calling thread. Setting for
     next execve() call and the inheritance bit are all OR-ed together.