| Message ID | 20230601095355.1168910-1-ism.hong@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 9a7e8ec0d4cc64870ea449b4fce5779b77496cbb |
| Headers | show |
| Series | riscv: perf: Fix callchain parse error with kernel tracepoint events | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Single patches do not need cover letters |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD ac9a78681b92 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 6 and now 6 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 221 this patch: 221 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 1388 this patch: 1388 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | CHECK: No space is necessary after a cast |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
Hello: This patch was applied to riscv/linux.git (fixes) by Palmer Dabbelt <palmer@rivosinc.com>: On Thu, 1 Jun 2023 17:53:55 +0800 you wrote: > For RISC-V, when tracing with tracepoint events, the IP and status are > set to 0, preventing the perf code parsing the callchain and resolving > the symbols correctly. > > ./ply 'tracepoint:kmem/kmem_cache_alloc { @[stack]=count(); }' > @: > { <STACKID4294967282> }: 1 > > [...] Here is the summary with links: - riscv: perf: Fix callchain parse error with kernel tracepoint events https://git.kernel.org/riscv/c/9a7e8ec0d4cc You are awesome, thank you!
On Thu, 01 Jun 2023 17:53:55 +0800, Ism Hong wrote: > For RISC-V, when tracing with tracepoint events, the IP and status are > set to 0, preventing the perf code parsing the callchain and resolving > the symbols correctly. > > ./ply 'tracepoint:kmem/kmem_cache_alloc { @[stack]=count(); }' > @: > { <STACKID4294967282> }: 1 > > [...] Applied, thanks! [1/1] riscv: perf: Fix callchain parse error with kernel tracepoint events https://git.kernel.org/palmer/c/9a7e8ec0d4cc Best regards,
diff --git a/arch/riscv/include/asm/perf_event.h b/arch/riscv/include/asm/perf_event.h index d42c901f9a97..665bbc9b2f84 100644 --- a/arch/riscv/include/asm/perf_event.h +++ b/arch/riscv/include/asm/perf_event.h @@ -10,4 +10,11 @@ #include <linux/perf_event.h> #define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs + +#define perf_arch_fetch_caller_regs(regs, __ip) { \ + (regs)->epc = (__ip); \ + (regs)->s0 = (unsigned long) __builtin_frame_address(0); \ + (regs)->sp = current_stack_pointer; \ + (regs)->status = SR_PP; \ +} #endif /* _ASM_RISCV_PERF_EVENT_H */
For RISC-V, when tracing with tracepoint events, the IP and status are set to 0, preventing the perf code parsing the callchain and resolving the symbols correctly. ./ply 'tracepoint:kmem/kmem_cache_alloc { @[stack]=count(); }' @: { <STACKID4294967282> }: 1 The fix is to implement perf_arch_fetch_caller_regs for riscv, which fills several necessary registers used for callchain unwinding, including epc, sp, s0 and status. It's similar to commit b3eac0265bf6 ("arm: perf: Fix callchain parse error with kernel tracepoint events") and commit 5b09a094f2fb ("arm64: perf: Fix callchain parse error with kernel tracepoint events"). With this patch, callchain can be parsed correctly as: ./ply 'tracepoint:kmem/kmem_cache_alloc { @[stack]=count(); }' @: { __traceiter_kmem_cache_alloc+68 __traceiter_kmem_cache_alloc+68 kmem_cache_alloc+354 __sigqueue_alloc+94 __send_signal_locked+646 send_signal_locked+154 do_send_sig_info+84 __kill_pgrp_info+130 kill_pgrp+60 isig+150 n_tty_receive_signal_char+36 n_tty_receive_buf_standard+2214 n_tty_receive_buf_common+280 n_tty_receive_buf2+26 tty_ldisc_receive_buf+34 tty_port_default_receive_buf+62 flush_to_ldisc+158 process_one_work+458 worker_thread+138 kthread+178 riscv_cpufeature_patch_func+832 }: 1 This patch works both on RV32/RV64. Signed-off-by: Ism Hong <ism.hong@gmail.com> --- arch/riscv/include/asm/perf_event.h | 7 +++++++ 1 file changed, 7 insertions(+)