| Message ID | 20230619180411.12946-1-palmer@rivosinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2] RISC-V: Document that V registers are clobbered on syscalls | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Single patches do not need cover letters |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD d5e45e810e0e |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 6 and now 6 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 8 this patch: 8 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 8 this patch: 8 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 20 this patch: 20 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 9 lines checked |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
Palmer Dabbelt <palmer@rivosinc.com> writes: > This is included in the ISA manual, but it's pretty common for bits of > the ISA manual that are actually ABI to change. So let's document it > explicitly. > > Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> > --- > Changes since v1 <20230614163534.18668-1-palmer@rivosinc.com>: > > * Remove the code change, just update the documentation. We might still > want to do something in the code, but that's still under discussion so > let's get the docs sorted out for now. > --- > Documentation/riscv/vector.rst | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/riscv/vector.rst b/Documentation/riscv/vector.rst > index 48f189d79e41..96f0fedece73 100644 > --- a/Documentation/riscv/vector.rst > +++ b/Documentation/riscv/vector.rst > @@ -130,3 +130,9 @@ processes in form of sysctl knob: > > Modifying the system default enablement status does not affect the enablement > status of any existing process of thread that do not make an execve() call. > + > +3. Vector Register State Across System Calls > +--------------------------------------------- > + > +As indicated by version 1.0 of the V extension, vector registers are clobbered > +by system calls. Maybe add a reference to the spec [1]? Regardless if that is added, or not: Reviewed-by: Björn Töpel <bjorn@rivosinc.com> [1] https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc
On Mon, 19 Jun 2023 11:37:38 PDT (-0700), bjorn@kernel.org wrote: > Palmer Dabbelt <palmer@rivosinc.com> writes: > >> This is included in the ISA manual, but it's pretty common for bits of >> the ISA manual that are actually ABI to change. So let's document it >> explicitly. >> >> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> >> --- >> Changes since v1 <20230614163534.18668-1-palmer@rivosinc.com>: >> >> * Remove the code change, just update the documentation. We might still >> want to do something in the code, but that's still under discussion so >> let's get the docs sorted out for now. >> --- >> Documentation/riscv/vector.rst | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/Documentation/riscv/vector.rst b/Documentation/riscv/vector.rst >> index 48f189d79e41..96f0fedece73 100644 >> --- a/Documentation/riscv/vector.rst >> +++ b/Documentation/riscv/vector.rst >> @@ -130,3 +130,9 @@ processes in form of sysctl knob: >> >> Modifying the system default enablement status does not affect the enablement >> status of any existing process of thread that do not make an execve() call. >> + >> +3. Vector Register State Across System Calls >> +--------------------------------------------- >> + >> +As indicated by version 1.0 of the V extension, vector registers are clobbered >> +by system calls. > > Maybe add a reference to the spec [1]? > > Regardless if that is added, or not: > Reviewed-by: Björn Töpel <bjorn@rivosinc.com> > > [1] https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc Seems reasonable, I just sent a v3
diff --git a/Documentation/riscv/vector.rst b/Documentation/riscv/vector.rst index 48f189d79e41..96f0fedece73 100644 --- a/Documentation/riscv/vector.rst +++ b/Documentation/riscv/vector.rst @@ -130,3 +130,9 @@ processes in form of sysctl knob: Modifying the system default enablement status does not affect the enablement status of any existing process of thread that do not make an execve() call. + +3. Vector Register State Across System Calls +--------------------------------------------- + +As indicated by version 1.0 of the V extension, vector registers are clobbered +by system calls.
This is included in the ISA manual, but it's pretty common for bits of the ISA manual that are actually ABI to change. So let's document it explicitly. Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> --- Changes since v1 <20230614163534.18668-1-palmer@rivosinc.com>: * Remove the code change, just update the documentation. We might still want to do something in the code, but that's still under discussion so let's get the docs sorted out for now. --- Documentation/riscv/vector.rst | 6 ++++++ 1 file changed, 6 insertions(+)