@@ -12,6 +12,10 @@
#include <net/checksum.h>
+#ifdef CONFIG_RISCV_ISA_V
+#include <riscv_vector.h>
+#endif
+
/* Default version is sufficient for 32 bit */
#ifndef CONFIG_32BIT
__sum16 csum_ipv6_magic(const struct in6_addr *saddr,
@@ -115,6 +119,108 @@ unsigned int __no_sanitize_address do_csum(const unsigned char *buff, int len)
offset = (csum_t)buff & OFFSET_MASK;
kasan_check_read(buff, len);
ptr = (const csum_t *)(buff - offset);
+#ifdef CONFIG_RISCV_ISA_V
+ if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
+ /*
+ * Vector is likely available when the kernel is compiled with
+ * vector support, so nop when vector is available and jump when
+ * vector is not available.
+ */
+ asm_volatile_goto(ALTERNATIVE("j %l[no_vector]", "nop", 0,
+ RISCV_ISA_EXT_v, 1)
+ :
+ :
+ :
+ : no_vector);
+ } else {
+ if (!__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_v))
+ goto no_vector;
+ }
+
+ len += offset;
+
+ vuint64m1_t prev_buffer;
+ vuint32m1_t curr_buffer;
+ unsigned int shift, cl, tail_seg;
+ csum_t vl, csum;
+ const csum_t *ptr;
+
+#ifdef CONFIG_32BIT
+ csum_t high_result, low_result;
+#else
+ csum_t result;
+#endif
+
+ // Read the tail segment
+ tail_seg = len % 4;
+ csum = 0;
+ if (tail_seg) {
+ shift = (4 - tail_seg) * 8;
+ csum = *(unsigned int *)((const unsigned char *)ptr + len - tail_seg);
+ csum = ((unsigned int)csum << shift) >> shift;
+ len -= tail_seg;
+ }
+
+ unsigned int start_mask = (unsigned int)(~(~0U << offset));
+
+ riscv_v_enable();
+ asm(".option push \n\
+ .option arch, +v \n\
+ vsetvli %[vl], %[len], e8, m1, ta, ma \n\
+ # clear out mask and vector registers since we switch up sizes \n\
+ vmclr.m v0 \n\
+ vmclr.m %[prev_buffer] \n\
+ vmclr.m %[curr_buffer] \n\
+ # Mask out the leading bits of a misaligned address \n\
+ vsetivli x0, 1, e64, m1, ta, ma \n\
+ vmv.s.x %[prev_buffer], %[csum] \n\
+ vmv.s.x v0, %[start_mask] \n\
+ vsetvli %[vl], %[len], e8, m1, ta, ma \n\
+ vmnot.m v0, v0 \n\
+ vle8.v %[curr_buffer], (%[buff]), v0.t \n\
+ j 2f \n\
+ # Iterate through the buff and sum all words \n\
+ 1: \n\
+ vsetvli %[vl], %[len], e8, m1, ta, ma \n\
+ vle8.v %[curr_buffer], (%[buff]) \n\
+ 2: \n\
+ vsetvli x0, x0, e32, m1, ta, ma \n\
+ vwredsumu.vs %[prev_buffer], %[curr_buffer], %[prev_buffer] \n\t"
+#ifdef CONFIG_32BIT
+ "sub %[len], %[len], %[vl] \n\
+ slli %[vl], %[vl], 2 \n\
+ add %[buff], %[vl], %[buff] \n\
+ bnez %[len], 1b \n\
+ vsetvli x0, x0, e64, m1, ta, ma \n\
+ vmv.x.s %[result], %[prev_buffer] \n\
+ addi %[vl], x0, 32 \n\
+ vsrl.vx %[prev_buffer], %[prev_buffer], %[vl] \n\
+ vmv.x.s %[high_result], %[prev_buffer] \n\
+ .option pop"
+ : [vl] "=&r"(vl), [prev_buffer] "=&vd"(prev_buffer),
+ [curr_buffer] "=&vd"(curr_buffer),
+ [high_result] "=&r"(high_result), [low_result] "=&r"(low_result)
+ : [buff] "r"(ptr), [len] "r"(len), [start_mask] "r"(start_mask),
+ [csum] "r"(csum));
+
+ high_result += low_result;
+ high_result += high_result < low_result;
+#else // !CONFIG_32BIT
+ "subw %[len], %[len], %[vl] \n\
+ slli %[vl], %[vl], 2 \n\
+ addw %[buff], %[vl], %[buff] \n\
+ bnez %[len], 1b \n\
+ vsetvli x0, x0, e64, m1, ta, ma \n\
+ vmv.x.s %[result], %[prev_buffer] \n\
+ .option pop"
+ : [vl] "=&r"(vl), [prev_buffer] "=&vd"(prev_buffer),
+ [curr_buffer] "=&vd"(curr_buffer), [result] "=&r"(result)
+ : [buff] "r"(ptr), [len] "r"(len), [start_mask] "r"(start_mask),
+ [csum] "r"(csum));
+#endif // !CONFIG_32BIT
+ riscv_v_disable();
+no_vector:
+#endif // CONFIG_RISCV_ISA_V
len = len + offset - sizeof(csum_t);
/*
This patch is not ready for merge as vector support in the kernel is limited. However, the code has been tested in QEMU so the algorithms do work. When Vector support is more mature, I will do more thorough testing of this code. It is written in assembly rather than using the GCC vector instrinsics because they did not provide optimal code. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> --- arch/riscv/lib/csum.c | 106 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+)