| Message ID | 20230918180646.1398384-2-apatel@ventanamicro.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | KVM RISC-V fixes for ONE_REG interface | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be fixes at HEAD 8eb8fe67e2c8 |
| conchuod/fixes_present | success | Fixes tag present in non-next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 5 and now 5 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 9 this patch: 9 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 9 this patch: 9 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 25 this patch: 25 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 8 lines checked |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | Fixes tag looks correct |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Mon, Sep 18, 2023 at 11:07 AM Anup Patel <apatel@ventanamicro.com> wrote: > > The ISA_EXT registers to enabled/disable ISA extensions for VCPU > are always available when underlying host has the corresponding > ISA extension. The copy_isa_ext_reg_indices() called by the > KVM_GET_REG_LIST API does not align with this expectation so > let's fix it. > > Fixes: 031f9efafc08 ("KVM: riscv: Add KVM_GET_REG_LIST API support") > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > arch/riscv/kvm/vcpu_onereg.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c > index 1b7e9fa265cb..e7e833ced91b 100644 > --- a/arch/riscv/kvm/vcpu_onereg.c > +++ b/arch/riscv/kvm/vcpu_onereg.c > @@ -842,7 +842,7 @@ static int copy_isa_ext_reg_indices(const struct kvm_vcpu *vcpu, > u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_ISA_EXT | i; > > isa_ext = kvm_isa_ext_arr[i]; > - if (!__riscv_isa_extension_available(vcpu->arch.isa, isa_ext)) > + if (!__riscv_isa_extension_available(NULL, isa_ext)) > continue; > > if (uindices) { > -- > 2.34.1 > Reviewed-by: Atish Patra <atishp@rivosinc.com>
On Mon, Sep 18, 2023 at 11:36:43PM +0530, Anup Patel wrote: > The ISA_EXT registers to enabled/disable ISA extensions for VCPU > are always available when underlying host has the corresponding > ISA extension. The copy_isa_ext_reg_indices() called by the > KVM_GET_REG_LIST API does not align with this expectation so > let's fix it. > > Fixes: 031f9efafc08 ("KVM: riscv: Add KVM_GET_REG_LIST API support") > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > arch/riscv/kvm/vcpu_onereg.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c > index 1b7e9fa265cb..e7e833ced91b 100644 > --- a/arch/riscv/kvm/vcpu_onereg.c > +++ b/arch/riscv/kvm/vcpu_onereg.c > @@ -842,7 +842,7 @@ static int copy_isa_ext_reg_indices(const struct kvm_vcpu *vcpu, > u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_ISA_EXT | i; > > isa_ext = kvm_isa_ext_arr[i]; > - if (!__riscv_isa_extension_available(vcpu->arch.isa, isa_ext)) > + if (!__riscv_isa_extension_available(NULL, isa_ext)) > continue; > > if (uindices) { > -- > 2.34.1 > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 1b7e9fa265cb..e7e833ced91b 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -842,7 +842,7 @@ static int copy_isa_ext_reg_indices(const struct kvm_vcpu *vcpu, u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_ISA_EXT | i; isa_ext = kvm_isa_ext_arr[i]; - if (!__riscv_isa_extension_available(vcpu->arch.isa, isa_ext)) + if (!__riscv_isa_extension_available(NULL, isa_ext)) continue; if (uindices) {
The ISA_EXT registers to enabled/disable ISA extensions for VCPU are always available when underlying host has the corresponding ISA extension. The copy_isa_ext_reg_indices() called by the KVM_GET_REG_LIST API does not align with this expectation so let's fix it. Fixes: 031f9efafc08 ("KVM: riscv: Add KVM_GET_REG_LIST API support") Signed-off-by: Anup Patel <apatel@ventanamicro.com> --- arch/riscv/kvm/vcpu_onereg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)